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- Hanho Lee
- ISCAS
- 2003
- Taesang Cho, Hanho Lee
- IEEE Transactions on Very Large Scale Integration…
- 2013
This paper presents a high-speed low-complexity modified radix-25 512-point fast Fourier transform (FFT) processor using an eight data-path pipelined approach for high rate wireless personal area… (More)
- Hanho Lee, Meng-Lin Yu, Leilei Song
- ISCAS
- 2000
- Jeesung Lee, Hanho Lee, Sang-in Cho, Sang-Sung Choi
- 2006 IEEE International Symposium on Circuits and…
- 2006
This paper presents the architecture design of a high-speed, low-complexity 128-point radix-24 FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture… (More)
- Hanho Lee
- IEEE International SOC Conference, 2004…
- 2004
Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this… (More)
- Minhyeok Shin, Hanho Lee
- 2008 IEEE International Symposium on Circuits and…
- 2008
In this paper, we present a novel high-speed low- complexity four data-path 128-point radix-24 FFT/IFFT processor for high-throughput MB-OFDM UWB systems. The high radix radix-24 multi-path delay… (More)
This paper presents a novel high-speed, low-complexity 128/64-point radix-24 FFT/IFFT processor for the applications in a high-throughput MIMO-OFDM systems. The high radix radix-24 multi-path delay… (More)
- Hanho Lee
- ISVLSI
- 2003
This paper presents a new area-efficient architrecture to implement the Euclidean algorithm, which is frequently used in Reed-Solomon decoders. The RS (255,239) decoder using the Euclidean algorithm… (More)
- Sangmin Kim, Gerald E. Sobelman, Hanho Lee
- IEEE Transactions on Very Large Scale Integration…
- 2011
A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle… (More)
- Seungbeom Lee, Chang-Seok Choi, Hanho Lee
- IEICE Electronic Express
- 2008
This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A highspeed two-parallel… (More)