Author pages are created from data sourced from our academic publisher partnerships and public sources.
- Publications
- Influence
High-speed VLSI architecture for parallel Reed-Solomon decoder
- Hanho Lee
- Computer Science
- Proceedings of the International Symposium on…
- 25 May 2003
TLDR
A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications
- Minhyeok Shin, Hanho Lee
- Computer Science
- IEEE International Symposium on Circuits and…
- 18 May 2008
TLDR
A High-Speed Low-Complexity Modified ${\rm Radix}-2^{5}$ FFT Processor for High Rate WPAN Applications
- Taesang Cho, Hanho Lee
- Computer Science
- IEEE Transactions on Very Large Scale Integration…
- 2013
TLDR
High-speed VLSI architecture for parallel Reed-Solomon decoder
- Hanho Lee
- Computer Science
- IEEE Trans. Very Large Scale Integr. Syst.
- 1 April 2003
TLDR
A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems
- Jeesung Lee, Hanho Lee
- Computer Science
- IEICE Trans. Fundam. Electron. Commun. Comput…
- 1 April 2008
TLDR
A power-aware scalable pipelined Booth multiplier
- Hanho Lee
- Computer Science
- IEEE International SOC Conference, . Proceedings.
- 30 November 2004
TLDR
A high-speed low-complexity Reed-Solomon decoder for optical communications
- Hanho Lee
- Computer Science
- IEEE Trans. Circuits Syst. II Express Briefs
- 15 August 2005
TLDR
VLSI design of Reed-Solomon decoder architectures
TLDR
A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems
TLDR
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes
- S. Kim, G. Sobelman, Hanho Lee
- Mathematics, Computer Science
- IEEE Transactions on Very Large Scale Integration…
- 1 June 2011
TLDR