• Publications
  • Influence
High-speed VLSI architecture for parallel Reed-Solomon decoder
  • Hanho Lee
  • Computer Science
  • Proceedings of the International Symposium on…
  • 25 May 2003
TLDR
This paper presents high-speed parallel RS(255,239) decoder architecture using a modified Euclidean algorithm for the high speed fiber optic systems. Expand
  • 81
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A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications
TLDR
In this paper, we present a novel high-speed low- complexity four data-path 128-point radix-24 FFT/IFFT processor for high-throughput MB-OFDM UWB systems. Expand
  • 91
  • 10
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A High-Speed Low-Complexity Modified ${\rm Radix}-2^{5}$ FFT Processor for High Rate WPAN Applications
TLDR
This paper presents a high-speed low-complexity modified radix-25 512-point fast Fourier transform (FFT) processor using an eight data-path pipelined approach for high rate wireless personal area network applications. Expand
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High-speed VLSI architecture for parallel Reed-Solomon decoder
  • Hanho Lee
  • Computer Science
  • IEEE Trans. Very Large Scale Integr. Syst.
  • 1 April 2003
TLDR
This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high speed multigigabit-per-second fiber optic systems. Expand
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  • 6
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A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems
TLDR
This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. Expand
  • 55
  • 5
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A power-aware scalable pipelined Booth multiplier
  • Hanho Lee
  • Computer Science
  • IEEE International SOC Conference, . Proceedings.
  • 30 November 2004
TLDR
This paper presents a low-power power-aware scalable pipelined Booth multiplier that makes use of the sharing common functional unit, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications. Expand
  • 79
  • 5
A high-speed low-complexity Reed-Solomon decoder for optical communications
  • Hanho Lee
  • Computer Science
  • IEEE Trans. Circuits Syst. II Express Briefs
  • 15 August 2005
TLDR
This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high- speed optical communications. Expand
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VLSI design of Reed-Solomon decoder architectures
TLDR
This paper presents VLSI implementations of an 8-error correcting (255, 239) Reed-Solomon (RS) decoder architecture for the optical fibre systems. Expand
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A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems
  • Hang Liu, Hanho Lee
  • Computer Science
  • APCCAS - IEEE Asia Pacific Conference on…
  • 1 November 2008
TLDR
This paper presents a novel high-speed, low-complexity 128/64-point radix-24 FFT/IFFT processor for the applications in a high-throughput MIMO-OFDM systems. Expand
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  • 4
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A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes
TLDR
A reduced-complexity low density parity check (LDPC) layered architecture is proposed using an offset permutation scheme in the switch networks. Expand
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