Hanho Lee

This paper presents high-speed parallel RS(255,239) decoder architecture using a modified Euclidean algorithm for the high speed fiber optic systems. Expand

In this paper, we present a novel high-speed low- complexity four data-path 128-point radix-24 FFT/IFFT processor for high-throughput MB-OFDM UWB systems. Expand

This paper presents a high-speed low-complexity modified radix-25 512-point fast Fourier transform (FFT) processor using an eight data-path pipelined approach for high rate wireless personal area network applications. Expand

This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high speed multigigabit-per-second fiber optic systems. Expand

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. Expand

This paper presents a low-power power-aware scalable pipelined Booth multiplier that makes use of the sharing common functional unit, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications. Expand

This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high- speed optical communications. Expand

This paper presents VLSI implementations of an 8-error correcting (255, 239) Reed-Solomon (RS) decoder architecture for the optical fibre systems. Expand

This paper presents a novel high-speed, low-complexity 128/64-point radix-24 FFT/IFFT processor for the applications in a high-throughput MIMO-OFDM systems. Expand

A reduced-complexity low density parity check (LDPC) layered architecture is proposed using an offset permutation scheme in the switch networks. Expand