Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture

@article{Kshirsagar2013ImplementationOP,
  title={Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture},
  author={Rahul D. Kshirsagar and E. V. Aishwarya and Ahire Shashank Vishwanath and Priyanga Jayakrishnan},
  journal={2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)},
  year={2013},
  pages={199-204}
}
The Booth multiplier is a very fast multiplier with minimum latencies. In this paper, a typical architecture of Booth Encoder and Wallace tree is presented, In which we have implemented pipelining at the intermediate nodes of the modules present in it. The architecture comprises of four modules, they are as follows, One's Complement generator, Booth Encoder, Partial product generator and Wallace tree adder accompanied by Ripple carry adder respectively. The Wallace tree adder and Booth… CONTINUE READING