Skip to search formSkip to main contentSkip to account menu

Bit slicing

Known as: Bit slice processors, Bit slice, Bit slice processor 
Bit slicing is a technique for constructing a processor from modules of smaller bit width. Each of these components processes one bit field or "slice… 
Wikipedia (opens in a new tab)

Related topics

Related topics

33 relations
1-bit architecture32-bit36-bit4-bit

Broader (1)

Digital electronics

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Design and Fabrication of a Three-Hopper Plantain Slicing Machine
Plantain is a semi-perishable crop and large quantity is wasted due to deterioration during the peak of harvest. To ensure food… 
2009
2009
Large matrix, small rank
For the problem of computing the rank of a matrix we have a complexity result and a practical implementation, both of which apply… 
2004
2004
Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories
Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and… 
2004
2004
Serial bit-stream analysis using quantum-dot cellular automata
Quasi-adiabatically switched quantum-dot cellular automata (QCA) devices present the opportunity to extend our efforts from the… 
2003
2003
Design of low-power content-addressable memory cell
Content addressable memory (CAM), a large amount of energy is generally expended charging and discharging most of the match lines… 
1997
1997
How good are slicing floorplans?
Given a set of modules with flexibility in shape, we show that there exists a slicing floorplan F such that area(F) = = 2 is the… 
1991
1991
Improved yield models for fault-tolerant random-access memory chips
  • C. Stapper
  • [Proceedings] International Workshop on Defect…
  • 1991
  • Corpus ID: 58291935
Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of… 
1988
1988
A bit-slice architecture for sigma-delta analog-to-digital converters
The sigma-delta analog-to-digital converters is based on filtering and undersampling by the digital section of the one-bit output… 
1985
1985
Test generation by activation and defect-drive (TEGAD)
1980
1980
Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement
This paper describes the circuit schemes used to substitute redundant storage locations for defective ones found during testing… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)