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BCDMOS
BCDMOS is a complex circuit composed of Bipolar, CMOS and LDMOS devices. Breakdown voltages can be as high as 750 V.
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Related topics
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6 relations
Analogue electronics
CMOS
Electronic circuit
Integrated circuit
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Papers overview
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2016
2016
12.8 Synchronized floating current mirror for maximum LED utilization in multiple-string linear LED drivers
Junsik Kim
,
S. Park
IEEE International Solid-State Circuits…
2016
Corpus ID: 5893033
High-voltage linear drivers for multiple-string LEDs have been widely used in general lighting due to their low cost, simplicity…
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2016
2016
Ultra-high precision bandgap voltage reference using a novel current trimming technique
Fei Lu
,
Z. Dong
,
+5 authors
Albert Z. H. Wang
IEEE International Conference on Solid-State and…
2016
Corpus ID: 21958415
This paper presents design of an ultra-high precision bandgap voltage reference circuit in a 180nm BCDMOS 1P6M process. A novel…
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2015
2015
자동차 스마트 정션 박스 소형화를 위한 0.18㎛ BCDMOS 기반 스위치 회로 설계
이욱준
,
권건오
,
임한상
,
신현철
2015
Corpus ID: 195611536
본 논문에서는 자동차 스마트 정션 박스(Smart Junction Box: SJB)의 소형화를 위하여 기존에 단위소자로 구성되어 있던 Enable 스위치 회로의 ASIC화를 위한 연구를 수행하였다. Enable…
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2015
2015
Highly Efficient Envelope-Tracking Modulator Over Wide Output Power Range for Dual-Mode Power Amplifier
Jooseung Kim
,
Seungbeom Koo
,
Yunsung Cho
,
Byungjoon Park
,
Kyunghoon Moon
,
Bumman Kim
2015
Corpus ID: 30747142
This paper presents a highly efficient envelope-tracking (ET) modulator over wide output power range. The ET modulator is…
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2015
2015
Switch Circuit Design in 0.18㎛ BCDMOS for Small Form Factor Automotive Smart Junction Box
U. Lee
,
Geono Kwon
,
Hansang Lim
,
Hyunchol Shin
2015
Corpus ID: 62577406
This paper presents a design of the enable switch circuit, which is consist of discrete device at smart junction box(SJB) board…
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2013
2013
입력전압을 감지하지 않는 전류연속/임계동작모드 Active Power Factor Correction Circuit
노용성
,
유창식
2013
Corpus ID: 60930903
본 논문에서는 입력전압을 감지하지 않는 전류연속/임계동작모드 active power factor correction(PFC) circuit을 제안하였다. 기존의 입력전압을 감지하지 않는 PFC circuit…
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2011
2011
The Process Integration of High-Voltage BCDMOS IC
Zhang Guo-guang
2011
Corpus ID: 63743503
The structure and process of high voltage BCDMOS are studied and optimized in this paper.The BCDMOS IC includes NPN,PNP,NMOS,PMOS…
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2010
2010
LDO Design Methodology and an Intelligent Power Management Sub-System IC for CDMA Handsets
T. Wakimoto
IEICE transactions on electronics
2010
Corpus ID: 45850947
This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub…
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2003
2003
Atmel ’ s Platform-based Methodology for System-on-Chip Design
P. Bishop
2003
Corpus ID: 14322114
The semiconductor industry is moving towards nanoscale technology with IC transistor counts attaining the hundreds of millions…
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2002
2002
The Advanced RESURF Structure to Improve On-Resistance in BCDMOS
C. J. Kim
,
Y. Choi
,
+4 authors
Fairchild
2002
Corpus ID: 195059363
In this paper, We report the novel RESURF structure of LDMOS TR with the p-bottom layer to improve OnResistance. The developed…
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