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Wafer-level packaging
Known as:
WL-CSP
, WLNSP
, WLP
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Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional…
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Related topics
Related topics
9 relations
Chip-scale package
Integrated circuit
List of integrated circuit packaging types
Smartphone
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging
J. Lau
,
Ming Li
,
+23 authors
Ricky S. W. Lee
IEEE Transactions on Components, Packaging, and…
2018
Corpus ID: 46954343
The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die…
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Highly Cited
2017
Highly Cited
2017
Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging
J. Lau
,
Ming Li
,
+19 authors
Q. Yong
IEEE Transactions on Components, Packaging, and…
2017
Corpus ID: 20155290
In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed…
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Highly Cited
2016
Highly Cited
2016
InFO (Wafer Level Integrated Fan-Out) Technology
C. Tseng
,
Chung-Shi Liu
,
Chi-Hsi Wu
,
Douglas Yu
Electronic Components and Technology Conference
2016
Corpus ID: 31903044
A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application…
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Highly Cited
2016
Highly Cited
2016
Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications
V. S. Rao
,
C. T. Chong
,
+5 authors
Y. Y. Liang
Electronic Components and Technology Conference
2016
Corpus ID: 11739579
Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of…
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Review
2011
Review
2011
Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review
Sang Hwui Lee
,
Kuan-Neng Chen
,
James J.-Q. Lu
Journal of microelectromechanical systems
2011
Corpus ID: 15512836
This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an important…
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Highly Cited
2010
Highly Cited
2010
Next generation eWLB (embedded wafer level BGA) packaging
Yonggang Jin
,
X. Baraton
,
+5 authors
A. Bahr
Electronic Packaging Technology Conference
2010
Corpus ID: 20500476
Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain…
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Review
2008
Review
2008
Wafer level packaging of MEMS
M. Esashi
TRANSDUCERS - International Solid-State Sensors…
2008
Corpus ID: 2066549
Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and…
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Highly Cited
2008
Highly Cited
2008
Embedded Wafer Level Ball Grid Array (eWLB)
M. Brunnbauer
,
Thorsten Meyer
,
Gerald Ofner
,
K. Mueller
,
R. Hagen
Electronic Packaging Technology Conference
2008
Corpus ID: 11728085
Wafer Level Packaging (fan-in WLB, Wafer Level Ball Grid Array) is the upcoming future packaging technology with many advantages…
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Highly Cited
2008
Highly Cited
2008
Embedded Wafer Level Ball Grid Array (eWLB)
M. Brunnbauer
,
T. Meyer
,
G. Ofner
,
K. Mueller
,
R. Hagen
International Electronics Manufacturing…
2008
Corpus ID: 47432652
The main challenges of today's device packaging are miniaturization, continuously increasing operating frequencies/high data…
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Highly Cited
2004
Highly Cited
2004
Localized induction heating solder bonding for wafer level MEMS packaging
Hsueh-An Yang
,
Mingching Wu
,
W. Fang
17th IEEE International Conference on Micro…
2004
Corpus ID: 10575410
This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was…
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