Translation lookaside buffer

Known as: ITLB, TLB, Translation-lookaside buffer 
A Translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location. It is a part of the… (More)
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Papers overview

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2016
2016
A multiprocessor which shares the memory among processors and uses multiples translation lookaside buffers (TLBs) can face… (More)
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2012
2012
The communication latency between the cores in multiprocessor architectures differs depending on the memory hierarchy and the… (More)
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2006
2006
Power consumption is now becoming equally as important as performance in microprocessor systems. Two major sources of processor… (More)
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2003
2003
Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction… (More)
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Highly Cited
1994
Highly Cited
1994
A number of interacting trends in operating system structure, processor architecture, and memory systems are increasing both the… (More)
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1990
1990
Nine solutions to the cache consistency problem for shared-memory multiprocessors with multiple translation-lookaside buffers… (More)
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1990
1990
A 64-entry, fully associative translation lookaside buffer (TLB) which has pin-to-pin address translation time of 3.6 ns is… (More)
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Highly Cited
1989
Highly Cited
1989
We discuss the translation lookaside buffer (TLB) consistency problem for multiprocessors, and introduce the Mach shootdown… (More)
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1989
1989
Operating systems for most current shared-memory multiprocessors must maintain translation lookaside buffer (TLB) consistency… (More)
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1988
1988
Most current computer architectures use a high−speed cache to translate user virtual addresses into physical memory addresses. On… (More)
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