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Translation lookaside buffer

Known as: ITLB, TLB, Translation-lookaside buffer 
A Translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location. It is a part of the… 
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Related topics

Related topics

50 relations
AMD 10hARM architectureAlpha 21064Athlon

Broader (2)

Central processing unitComputer memory

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Inconsistency in translation lookaside buffer
A multiprocessor which shares the memory among processors and uses multiples translation lookaside buffers (TLBs) can face… 
Highly Cited
2010
Highly Cited
2010
Characterization of Metamorphic GaAsP/Si Materials and Devices for Photovoltaic Applications
GaAsyP1-y anion-sublattice compositionally graded buffers and device structures were grown directly on Si(100) substrates by way… 
2010
2010
Performance of multi-process and multi-thread processing on multi-core SMT processors
Many modern high-performance processors support multiple hardware threads in the form of multiple cores and SMT (Simultaneous… 
2007
2007
I/O processing in a virtualized platform: a simulation-driven approach
Virtualization provides levels of execution isolation and service partition that are desirable in many usage scenarios, but its… 
2006
2006
A Study of Power Trade-offs in Translation Lookaside Buffer Structures
Power consumption is now becoming equally as important as performance in microprocessor systems. Two major sources of processor… 
2006
2006
Can Moisture Buffer Performance be Estimated from Sorption Kinetics?
This article describes the research on the moisture buffering effect of building materials. A set of experiments on samples of… 
2005
2005
Two-step growth of ZnO films on silicon by atomic layer deposition
Two-step growth of ZnO by atomic layer deposition at low temperatures was performed to grow quality ZnO films on silicon… 
Highly Cited
2000
Highly Cited
2000
Using complete system simulation to characterize SPECjvm98 benchmarks
Complete system simulation to understand the influence of architecture and operating systems on application execution has been… 
1994
1994
Address space sparsity and fine granularity
To fully exploit the potential of large address spaces, e.g. 264-byte, the sparsity problem has to be solved in an efficient… 
Highly Cited
1993
Highly Cited
1993
Integrated management of priority inversion in Real-Time Mach
Synchronization and communication are two common sources of priority inversion which may make the behavior of systems… 
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