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Leakage Current: Moore's Law Meets Static Power
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from…
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
- Feihui Li, C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, M. Kandemir
- Computer Science33rd International Symposium on Computer…
- 1 May 2006
A router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory are proposed that demonstrate that a 3D L2 memory architecture generates much better results than the conventional two-dimensional designs under different number of layers and vertical connections.
Analysis of error recovery schemes for networks on chips
- S. Murali, T. Theocharides, N. Vijaykrishnan, M. Irwin, L. Benini, G. Micheli
- Computer ScienceIEEE Design & Test of Computers
- 1 September 2005
This article explores error control mechanisms at the data link and network layers and presents the schemes' architectural details to investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
This work forms the relationship between retention-time and write-latency, and finds optimal retention- time for architecting an efficient cache hierarchy using STT-RAM to overcome high write latency and energy problems.
The design and use of simplePower: a cycle-accurate energy estimation tool
- W. Ye, N. Vijaykrishnan, M. Kandemir, M. Irwin
- Computer ScienceProceedings - Design Automation Conference
- 1 June 2000
This paper uses the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization on the datapath, memory and on-chip bus energy, respectively.
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
- C. Nicopoulos, Dongkook Park, Jongman Kim, N. Vijaykrishnan, M. Yousif, C. Das
- 9 December 2006
A novel unified buffer structure, called the dynamic virtual channel regulator (ViChaR), which dynamically allocates virtual channels and buffer resources according to network traffic conditions and maximizes throughput by dispensing a variable number of VCs on demand is introduced.
Architecture exploration for ambient energy harvesting nonvolatile processors
- Kaisheng Ma, Yang Zheng, N. Vijaykrishnan
- Computer ScienceInternational Symposium on High-Performance…
- 9 March 2015
The simulation platform in this paper is calibrated using measured results from a fabricated nonvolatile processor and used to explore the design space for a nonVolatile processor with different architectures, different input power sources, and policies for maximizing forward progress.
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
- R. Das, S. Eachempati, Asit K. Mishra, N. Vijaykrishnan, C. Das
- Computer ScienceIEEE 15th International Symposium on High…
- 6 March 2009
A novel router micro-architecture is proposed, called XShare, which exploits data value locality and bimodal traffic characteristics of CMP applications to transfer multiple small flits over a single channel, and helps in enhancing the network throughput by 35%, providing a latency reduction of 14% with synthetic traffic, and improving IPC on an average 4% with application workloads.
Exploring Fault-Tolerant Network-on-Chip Architectures
- Dongkook Park, C. Nicopoulos, Jongman Kim, N. Vijaykrishnan, C. Das
- EngineeringInternational Conference on Dependable Systems…
- 25 June 2006
This paper examines the impact of transient failures on the reliability of on-chip interconnects and develops comprehensive counter-measures to either prevent or recover from them and proposes several novel schemes to remedy various kinds of soft error symptoms.
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
A novel partially-connected 3D crossbar structure, called the 3D Dimensionally-Decomposed (DimDe) Router, is proposed, which provides a good tradeoff between circuit complexity and performance benefits.