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Leakage Current: Moore's Law Meets Static Power
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises fromExpand
Analysis of error recovery schemes for networks on chips
This article explores error control mechanisms at the data link and network layers and presents the schemes' architectural details to investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms. Expand
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
This work forms the relationship between retention-time and write-latency, and finds optimal retention- time for architecting an efficient cache hierarchy using STT-RAM to overcome high write latency and energy problems. Expand
The design and use of simplePower: a cycle-accurate energy estimation tool
This paper uses the use of SimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization on the datapath, memory and on-chip bus energy, respectively. Expand
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
A router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory are proposed that demonstrate that a 3D L2 memory architecture generates much better results than the conventional two-dimensional designs under different number of layers and vertical connections. Expand
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
A novel unified buffer structure, called the dynamic virtual channel regulator (ViChaR), which dynamically allocates virtual channels and buffer resources according to network traffic conditions and maximizes throughput by dispensing a variable number of VCs on demand is introduced. Expand
Architecture exploration for ambient energy harvesting nonvolatile processors
The simulation platform in this paper is calibrated using measured results from a fabricated nonvolatile processor and used to explore the design space for a nonVolatile processor with different architectures, different input power sources, and policies for maximizing forward progress. Expand
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
A novel router micro-architecture is proposed, called XShare, which exploits data value locality and bimodal traffic characteristics of CMP applications to transfer multiple small flits over a single channel, and helps in enhancing the network throughput by 35%, providing a latency reduction of 14% with synthetic traffic, and improving IPC on an average 4% with application workloads. Expand
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
A novel partially-connected 3D crossbar structure, called the 3D Dimensionally-Decomposed (DimDe) Router, is proposed, which provides a good tradeoff between circuit complexity and performance benefits. Expand
A low latency router supporting adaptivity for on-chip interconnects
This work simulates and evaluates the proposed router architecture which utilizes adaptive routing while maintaining low latency, and results indicate that the architecture is effective in balancing the performance and energy of NoC designs. Expand