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Tomasulo algorithm

Known as: Tomasulo, Tomasulo's algorithm, Tomasulo-architecture CPU 
Tomasulo’s algorithm is a computer architecture hardware algorithm for dynamic scheduling of instructions that allows out-of-order execution… 
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Related topics

Related topics

15 relations
AlgorithmArithmetic logic unitClassic RISC pipelineComputer architecture

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility
In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to… 
2007
2007
A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
A scalable, distributed, processor architecture is presented that emphasizes on high performance computing for digital signal… 
Review
2006
Review
2006
Analyzing Performance and Meaning in Film
THE IDEA FOR THIS SPECIAL ISSUE of the journal of Film and Video evolved over the past few years from stimulating interaction at… 
2005
2005
A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware
Abstract machines bridge the gap between a programming language and real machines. This paper proposes a general purpose tagged… 
1999
1999
Verifying Tomasulo's algorithm by refinement
  • T. AronsA. Pnueli
  • Proceedings Twelfth International Conference on…
  • 1999
  • Corpus ID: 35710033
In this paper Tomasulo's algorithm for out-of-order execution is shown to be a refinement of the sequential instruction execution… 
1999
1999
Results of the Verification of a Complex Pipelined Machine Model
Using a theorem prover, we have verified a microprocessor design, FM9801. We define our correctness criterion for processors with… 
1999
1999
A Proof of Correctness of a Processor Implementing Tomasulo's Algorithm without a Reorder Buffer
The Completion Functions Approach was proposed in [HSG98] as a systematic way to decompose the proof of correctness of pipelined… 
1995
1995
INCREASING RELIABILITY OF SMD TANTALUM CAPACITORS IN LOW IMPEDANCE APPLICATIONS
High dv/dt conditions in low impedance circuits using surface mount tantalum capacitors is discussed. Circuit designs utilizing… 
1985
1985
Implementation of precise interrupts in pipelined processors
An interrupt is precise if the saved process state corresponds with the sequential model of program execution where one… 
1982
1982
Dynamic detection of concurrency in DEL instruction streams
Detection of concurrency in Directly Executed Languages (DEL) is investigated. It is theorized that if DELs provide a minimal… 
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