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T-RAM
Thyristor RAM (T-RAM) is a new (2009) type of random-access memory invented and developed by T-RAM Semiconductor, which departs from the usual…
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Related topics
Related topics
5 relations
Floating body effect
Memory cell (binary)
Random-access memory
Static random-access memory
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
On the T-RAM and FED-RAM memory mechanism
A. Z. Badwan
,
Qiliang Li
,
D. Ioannou
IEEE SOI-3D-Subthreshold Microelectronics…
2015
Corpus ID: 27357252
We take a closer look on the memory mechanism (“store”) of the T-RAM and FED-RAM memory cells, with the help of extensive…
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2009
2009
Reliability of thyristor-based memory cells
C. Salling
,
Kevin Yang
,
+4 authors
S. Robins
IEEE International Reliability Physics Symposium
2009
Corpus ID: 33665907
This is the first published study of the reliability of Thyristor-based high-speed memories. The T-RAM (Thyristor-based Random…
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2007
2007
Thyristor RAM (T-RAM): A high-speed high-density embedded memory technology for nano-scale CMOS
F. Nemati
IEEE Hot Chips Symposium
2007
Corpus ID: 41650221
This article consists of a collection of slides from the author's conference presentation on T-RAM Semiconductor's Thyristor RAM…
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2006
2006
Optimization of Nanoscale Thyristors on SOI for High-Performance High-Density Memories
K. Yang
,
R.N. Gupta
,
+6 authors
S. Robins
IEEE international SOI Conferencee Proceedings
2006
Corpus ID: 32419600
In this paper, methods for achieving a manufacturable TCCT on SOI with excellent thermal stability and fast switching speed are…
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2005
2005
Optimization of substrate doping for back-gate control in SOI T-RAM memory technology
M. Ershov
,
F. Nemati
,
+8 authors
S. Robins
IEEE International SOI Conference Proceedings
2005
Corpus ID: 10416962
This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate…
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2005
2005
Integrated circuits and manufacturing DRAM and NAND flash
C. Mazure
,
T. Nakabayashi
IEEE InternationalElectron Devices Meeting…
2005
Corpus ID: 31787593
The first two papers take advantage of SOI substrates to propose capacitor-less DRAM architectures. The work by Minami, et al…
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2004
2004
Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs
F. Nemati
,
Hyun-jin Cho
,
+5 authors
V. Gopalakrishnan
IEDM Technical Digest. IEEE International…
2004
Corpus ID: 28778017
Major advancements in T-RAM cell manufacturability are reported. A fully planar implementation of a T-RAM cell is presented…
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