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Systolic array
Known as:
Array
, SSA
, Super systolic array
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In parallel computer architectures, a systolic array is a homogeneous network of tightly coupled data processing units (DPUs) called cells or nodes…
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Related topics
Related topics
49 relations
Address space
Algorithm
Anton (computer)
Array data structure
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Broader (2)
Parallel computing
Reconfigurable computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2003
Highly Cited
2003
Investigation of different fading forecast schemes for flat fading radio channels
S. Semmelrodt
,
R. Kattenbach
IEEE 58th Vehicular Technology Conference. VTC…
2003
Corpus ID: 61528345
After a brief introduction explaining the motivation for predicting the mobile radio channel both a deterministic channel model…
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2003
2003
Systolic array
H. Kung
2003
Corpus ID: 65001512
Systolic arrays are a family of parallel computer architectures capable of using a very large number of processors simultaneously…
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1990
1990
Systolic array for nonlinear multidimensional interpolation using radial basis functions
D. Broomhead
,
Richard D. Jones
,
J. McWhirter
,
T. Shepherd
1990
Corpus ID: 108446790
A fully systolic network is proposed for rapid and efficient multidimensional interpolation using radial basis functions (RBFs…
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Highly Cited
1989
Highly Cited
1989
Efficient one-dimensional systolic array realization of the discrete Fourier transform
J. Beraldin
,
T. Aboulnasr
,
W. Steenaart
1989
Corpus ID: 62729141
A one-dimensional systolic array realizing the discrete Fourier transform (DFT) of nonstop input sequences is presented. Two…
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Highly Cited
1987
Highly Cited
1987
Guest Editors' Introduction: Systolic Arrays-From Concept to Implementation
J. Fortes
,
B. Wah
Computer
1987
Corpus ID: 27080100
Systolic arrays are the result of advances in semiconductor technology and of applications that require extensive throughput…
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1987
1987
A systolic architecture for computation of the manipulator inertia matrix
Masoud Amin-Javaheri
,
D. Orin
Proceedings. IEEE International Conference on…
1987
Corpus ID: 38923354
Systolic architectures consisting of 1, N, and N(N + 1)/2 processors are presented for computing the inertia matrix. A VLSI-based…
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1986
1986
Systolic array synthesis: computability and time cones
J. Delosme
,
Ilse C. F. Ipsen
1986
Corpus ID: 118503496
Abstract : Many important algorithms in signal and image processing, speech and pattern recognition of matrix computations…
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1984
1984
OPTIMISED BIT LEVEL SYSTOLIC ARRAY FOR CONVOLUTION.
J. McCanny
,
J. McWhirter
,
K. Wood
1984
Corpus ID: 62721308
A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and…
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1984
1984
Application of a systolic array to adaptive beamforming
C. Ward
,
A. J. Robson
,
P. Hargrave
,
J. McWhirter
1984
Corpus ID: 120971997
The paper describes a new technique for adaptive antenna beamforming. By analysing the adaptive antenna as a least-squares…
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Highly Cited
1981
Highly Cited
1981
A Two-Level Pipelined Systolic Array for Convolutions
H. T. Kung
,
Lawrence M. Ruane
,
David W. L. Yen
1981
Corpus ID: 59827955
Pipelining computations over a large array of cells has been an important feature of systolic arrays. To achieve even higher…
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