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Systolic array

Known as: Array, SSA, Super systolic array 
In parallel computer architectures, a systolic array is a homogeneous network of tightly coupled data processing units (DPUs) called cells or nodes… 
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Papers overview

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Highly Cited
2018
Highly Cited
2018
  • J. CongJie Wang
  • IEEE/ACM International Conference on Computer…
  • 2018
  • Corpus ID: 51997145
Automatic systolic array generation has long been an interesting topic due to the need to reduce the lengthy development cycles… 
Highly Cited
2018
Highly Cited
2018
Systolic Arrays are one of the most popular compute substrates within Deep Learning accelerators today, as they provide extremely… 
Highly Cited
2017
Highly Cited
2017
Convolutional neural networks (CNNs) have been widely applied in many deep learning applications. In recent years, the FPGA… 
Highly Cited
1987
Highly Cited
1987
LUSTRE is a synchronous data-flow language for programming systems which interact with their environments in real-time. After an… 
Highly Cited
1986
Highly Cited
1986
A technique for partitioning and mapping algorithms into VLSI systolic arrays is presented in this paper. Algorithm partitioning… 
Highly Cited
1984
Highly Cited
1984
  • P. Quinton
  • International Symposium on Computer Architecture
  • 1984
  • Corpus ID: 16129075
We describe a systematic method for the design of systolic arrays. This method may be used for algorithms that can be expressed… 
Highly Cited
1983
Highly Cited
1983
A systolic array for performing recursive least-squares minimization is desc/ performs an orthogonal triangularization of the… 
Highly Cited
1983
Highly Cited
1983
  • D. Moldovan
  • Proceedings of the IEEE
  • 1983
  • Corpus ID: 7517251
This paper is concerned with the mapping of cyclic loop algorithms into special-purpose VLSI arrays. The mapping procedure is… 
Highly Cited
1982
Highly Cited
1982
Given an n x p matrix X with p < n, matrix triangularization, or triangularization in short, is to determine an n x n nonsingular… 
Highly Cited
1982
Highly Cited
1982
This paper describes and analyzes several algorithms for constructing systolic array networks from cells on a silicon wafer. Some…