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Systolic array
Known as:
Array
, SSA
, Super systolic array
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In parallel computer architectures, a systolic array is a homogeneous network of tightly coupled data processing units (DPUs) called cells or nodes…
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Related topics
Related topics
49 relations
Address space
Algorithm
Anton (computer)
Array data structure
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Broader (2)
Parallel computing
Reconfigurable computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Frequent itemset mining using cellular learning automata
M. Sohrabi
,
Reza Roshani
Computers in Human Behavior
2017
Corpus ID: 32951077
Highly Cited
2007
Highly Cited
2007
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders
Seungbeom Lee
,
Hanho Lee
IEEE International Symposium on Circuits and…
2007
Corpus ID: 3916583
This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm…
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Highly Cited
2003
Highly Cited
2003
Investigation of different fading forecast schemes for flat fading radio channels
S. Semmelrodt
,
R. Kattenbach
IEEE 58th Vehicular Technology Conference. VTC…
2003
Corpus ID: 61528345
After a brief introduction explaining the motivation for predicting the mobile radio channel both a deterministic channel model…
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Highly Cited
1997
Highly Cited
1997
Unified systolic arrays for computation of the DCT/DST/DHT
Sung Bum Pan
,
Rae-Hong Park
IEEE Trans. Circuits Syst. Video Technol.
1997
Corpus ID: 14780433
We propose unified systolic arrays for computation of the one-dimensional (1-D) and two-dimensional (2-D) discrete cosine…
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Highly Cited
1992
Highly Cited
1992
SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine
U. Ramacher
J. Parallel Distributed Comput.
1992
Corpus ID: 29294114
1992
1992
A Processor-Time-Minimal Systolic Array for Transitive Closure
C. Scheiman
,
P. Cappello
IEEE Trans. Parallel Distributed Syst.
1992
Corpus ID: 36237472
Using a directed acyclic graph (DAG) model of algorithms, the authors focus on processor-time-minimal multiprocessor schedules…
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Highly Cited
1991
Highly Cited
1991
A unified systolic array for discrete cosine and sine transforms
Long-Wen Chang
,
Ming-Chang Wu
IEEE Transactions on Signal Processing
1991
Corpus ID: 206468006
A linear systolic array for the discrete cosine transform, discrete sine transform, and their inverses is developed. It generates…
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1988
1988
The design of a systolic array with tags input
C. Jen
,
Huai-Yi Hsu
., IEEE International Symposium on Circuits and…
1988
Corpus ID: 56731987
A systolic architecture, called systolic arrays with tags input (SATIN), is proposed. Not only data but also tags are pumped into…
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1987
1987
A parallel image segmentation algorithm using relaxation with varying neighborhoods and its mapping to array processors
H. Derin
,
C. Won
Computer Vision Graphics and Image Processing
1987
Corpus ID: 34708578
Highly Cited
1981
Highly Cited
1981
A Two-Level Pipelined Systolic Array for Convolutions
H. T. Kung
,
Lawrence M. Ruane
,
David W. L. Yen
1981
Corpus ID: 59827955
Pipelining computations over a large array of cells has been an important feature of systolic arrays. To achieve even higher…
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