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Subtractor
Known as:
Subtracter (electronics)
, Full subtractor
, Subtractor (electronics)
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In electronics, a subtractor can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with…
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Related topics
Related topics
6 relations
Adder (electronics)
Adder–subtractor
Adding machine
Karnaugh map
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
A Second-Order Bandpass $\Delta\Sigma$ Time-to-Digital Converter With Negative Time-Mode Feedback
S. Ziabakhsh
,
G. Gagnon
,
G. Roberts
IEEE Transactions on Circuits and Systems Part 1…
2019
Corpus ID: 84186742
This paper presents an all-digital bandpass <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma $ </tex-math></inline…
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2015
2015
Memristor based N-bits redundant binary adder
A. A. El-Slehdar
,
A. Fouad
,
A. Radwan
Microelectronics Journal
2015
Corpus ID: 35230598
2015
2015
A fully integrated 6-bit vector-sum phase shifter in 0.18 um CMOS
E. V. Balashov
,
I. Rumyancev
International Siberian Conference on Control and…
2015
Corpus ID: 21319759
This paper presents a fully integrated vector-sum phase shifter with a 6-bit digital control in 0.18 um CMOS technology. The…
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2013
2013
The fast recursive computation of Tchebichef moment and its inverse transform based on Z-transform
Barmak Honarvar
,
R. Paramesran
,
C. Lim
Digit. Signal Process.
2013
Corpus ID: 16710518
2012
2012
Design of single precision float adder (32-bit numbers) according to IEEE 754 standard using VHDL
Arturo Barrabés Castillo
2012
Corpus ID: 58229022
Projecte realitzat en el marc d'un programa de mobilitat amb la Slovenska Technicka Univerzita v Bratislave, Fakulta…
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2010
2010
A decimal floating-point fused-multiply-add unit
R. Samy
,
H. Fahmy
,
R. Raafat
,
A. Mohamed
,
Tarek ElDeeb
,
Yasmin Farouk
53rd IEEE International Midwest Symposium on…
2010
Corpus ID: 2145225
This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit…
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2010
2010
Reversible Full Adder/Subtractor
Maii T. Emam
,
Layle A. A. Elsayed
XIth International Workshop on Symbolic and…
2010
Corpus ID: 15764076
This paper proposes two novel designs of Adder/Subtractor using reversible logic gates. The first design is an implementation of…
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1999
1999
Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm
A. Hiasat
,
H. Abdel-Aty-Zohdy
Computer/law journal
1999
Corpus ID: 28262931
In this paper we introduce a new algorithm for division in residue number system, which can be applied to any moduli set…
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1998
1998
High Linearity BiCMOS Multiplier/Transconductor Structures
N. Khachab
,
A. Al-Saqer
,
J. G. Varghese
1998
Corpus ID: 52410422
A new wide-input range BiCMOS analog multiplier is proposed basedon the triode and saturation region operation of the MOS…
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Highly Cited
1968
Highly Cited
1968
An approach to the implementation of digital filters
L. Jackson
,
J. Kaiser
,
H. McDonald
1968
Corpus ID: 62549199
An approach to the implementation of digital filters is presented that employs a small set of relatively simple digital circuits…
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