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Subtractor

Known as: Subtracter (electronics), Full subtractor, Subtractor (electronics) 
In electronics, a subtractor can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with… 
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Related topics

Related topics

6 relations
Adder (electronics)Adder–subtractorAdding machineKarnaugh map

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
A Second-Order Bandpass $\Delta\Sigma$ Time-to-Digital Converter With Negative Time-Mode Feedback
This paper presents an all-digital bandpass <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma $ </tex-math></inline… 
2015
2015
Performance improvement of QPSK modem implemented in FPGA
This paper proposes a Quadrature Phase Shift Keying (QPSK) using two different methods. QPSK is one of the forms of Phase Shift… 
2014
2014
CMOS Based Design Simulation Of Adder /Subtractor Using Different Foundries
:- In this paper a 4 bit parallel adder/subtractor circuit has been designed and analyzed. The circuit uses a controlled adder… 
2012
2012
A Hybrid Algorithm for Classification of Compressed ECG
Efficient compression reduces memory requirement in long term recording and reduces power and time requirement in transmission. A… 
2011
2011
Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation
Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis… 
2010
2010
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve
A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the… 
2006
2006
Implementation of Systolic RLS Adaptive Array Using FPGA and Its Performance Evaluation
In high-speed mobile radio communication, fast weight adaptation will be required. Recent progress of VLSI technology enables the… 
2006
2006
VHDL Implementation of the Fast Wavelet Transform
In this paper, a VHDL implementation of a decomposition unit based on Mallat's fast Wavelet Transform, which utilizes a two… 
1999
1999
Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm
In this paper we introduce a new algorithm for division in residue number system, which can be applied to any moduli set… 
1998
1998
High Linearity BiCMOS Multiplier/Transconductor Structures
A new wide-input range BiCMOS analog multiplier is proposed basedon the triode and saturation region operation of the MOS… 
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