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Subtractor
Known as:
Subtracter (electronics)
, Full subtractor
, Subtractor (electronics)
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In electronics, a subtractor can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with…
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6 relations
Adder (electronics)
Adder–subtractor
Adding machine
Karnaugh map
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Memristor based N-bits redundant binary adder
A. A. El-Slehdar
,
A. Fouad
,
A. G. Radwan
Microelectronics Journal
2015
Corpus ID: 35230598
2015
2015
Performance improvement of QPSK modem implemented in FPGA
Umesharaddy
,
B. Sujatha
International Conference on Smart Sensors and…
2015
Corpus ID: 41060135
This paper proposes a Quadrature Phase Shift Keying (QPSK) using two different methods. QPSK is one of the forms of Phase Shift…
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2015
2015
Efficient hardware design of N-point 1D-DCT for HEVC
J. D. Bolanos-Jojoa
,
Jaime Velasco-Medina
20th Symposium on Signal Processing, Images and…
2015
Corpus ID: 14347597
This work presents three hardware designs for N-point 1D-DCT used in high efficient video coding standard, which were designed…
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2012
2012
Design of single precision float adder (32-bit numbers) according to IEEE 754 standard using VHDL
Arturo Barrabés Castillo
2012
Corpus ID: 58229022
Projecte realitzat en el marc d'un programa de mobilitat amb la Slovenska Technicka Univerzita v Bratislave, Fakulta…
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2011
2011
Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation
S. Burignat
,
A. De Vos
International Conference on Mixed Design of…
2011
Corpus ID: 6958384
Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis…
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2010
2010
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve
K. Gaj
,
Soonhak Kwon
,
+5 authors
M. Rogawski
IEEE transactions on computers
2010
Corpus ID: 17669189
A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the…
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2006
2006
Implementation of Systolic RLS Adaptive Array Using FPGA and Its Performance Evaluation
Y. Yokoyama
,
Minseok Kim
,
H. Arai
IEEE Vehicular Technology Conference
2006
Corpus ID: 13100001
In high-speed mobile radio communication, fast weight adaptation will be required. Recent progress of VLSI technology enables the…
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2006
2006
Differential fuzzy filtering for adaptive line enhancement in spread spectrum communications
J. Bas
,
A. Pérez-Neira
,
M. Lagunas
Signal Processing
2006
Corpus ID: 29447714
1999
1999
Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm
A. Hiasat
,
H. Abdel-Aty-Zohdy
Computer/law journal
1999
Corpus ID: 28262931
In this paper we introduce a new algorithm for division in residue number system, which can be applied to any moduli set…
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1998
1998
High Linearity BiCMOS Multiplier/Transconductor Structures
N. Khachab
,
A. Al-Saqer
,
J. G. Varghese
1998
Corpus ID: 52410422
A new wide-input range BiCMOS analog multiplier is proposed basedon the triode and saturation region operation of the MOS…
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