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Decimal floating-point multiplication became important in many commercial applications. This paper presents a fully parallel Decimal64 floating point multiplier compliant to IEEE 754r standard. The proposed multiplier possesses novel methods to target low latency. The proposed design is based on previously published fixed point multiplier [1]. Several(More)
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the(More)
Floating-point representation can support a much wider range of values over fixed point representation. The performance of decimal floating-point operations is an important measure in many application domains such as financial, commercial, and internet-based computations. In this research, an iterative decimal floating-point multiplier design in IEEE(More)
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