Yasmin Farouk

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Decimal floating-point multiplication became important in many commercial applications. This paper presents a fully parallel Decimal64 floating point multiplier compliant to IEEE 754r standard. The proposed multiplier possesses novel methods to target low latency. The proposed design is based on previously published fixed point multiplier [1]. Several(More)
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiply-add, division, and square root. It stresses the importance of energy savings achieved by hardware implementations of the IEEE standard for decimal floating point. To the best of the(More)
Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fusedmultiply-add compliant with(More)
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