Strain engineering

Known as: Dual Stress Liner, Dual stress, Strained engineering 
Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are… (More)
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Papers overview

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Highly Cited
2009
Highly Cited
2009
Among many remarkable qualities of graphene, its electronic properties attract particular interest owing to the chiral character… (More)
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Highly Cited
2008
Highly Cited
2008
Flexible electronics, extremely sensitive sensors, strained-silicon technology, andmacromolecule separation, are only a few… (More)
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2007
2007
Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator… (More)
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Highly Cited
2006
Highly Cited
2006
We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate… (More)
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Highly Cited
2006
Highly Cited
2006
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion… (More)
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Review
2006
Review
2006
This work reviews the current progress in high-mobility strained MOSFETs and covers the latest developments in strain engineering… (More)
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2006
2006
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation… (More)
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2005
2005
A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance… (More)
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Highly Cited
2003
Highly Cited
2003
We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain… (More)
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2003
2003
A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described… (More)
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