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Software testability
Software testability is the degree to which a software artifact (i.e. a software system, software module, requirements- or design document) supports…
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Related topics
Related topics
10 relations
Finite-state machine
Matthew Hennessy
Non-functional requirement
Portability testing
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2016
Highly Cited
2016
A Markov Chain-Based Testability Growth Model With a Cost-Benefit Function
Chenxu Zhao
,
K. Pattipati
,
Guanjun Liu
,
J. Qiu
,
K. Lv
,
Tianmei Li
IEEE Transactions on Systems, Man, and…
2016
Corpus ID: 33376412
In this paper, we propose a Markov chain-based testability growth model (TGM) for the just in-time fix program. This model can…
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Highly Cited
2006
Highly Cited
2006
Design for Testability
Laung-Terng Wang
,
X. Wen
,
Khader S. Abdel-Hafez
2006
Corpus ID: 60079306
Highly Cited
1999
Highly Cited
1999
A Programmable BIST Core for Embedded DRAM
Chih-Tsun Huang
,
Jing-Reng Huang
,
Chi-Feng Wu
,
Cheng-Wen Wu
,
Tsin-Yuan Chang
IEEE Design & Test of Computers
1999
Corpus ID: 28276441
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm…
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Highly Cited
1995
Highly Cited
1995
The Time-Triggered Approach to Real-Time System Design
H. Kopetz
1995
Corpus ID: 60928373
In this paper the basic assumptions that govern the design of timetriggered(TT) real-time systems are examined and the…
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Highly Cited
1994
Highly Cited
1994
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency
I. Harris
,
A. Orailoglu
Design Automation Conference
1994
Corpus ID: 5969484
The testability of a VLSI design is strongly affected by its register-transfer level (RTL) structure. Since the high-level…
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1994
1994
Retiming sequential circuits to enhance testability
S. Dey
,
S. Chakradhar
Proceedings of the ... IEEE VLSI Test Symposium
1994
Corpus ID: 7181041
This paper presents a technique to enhance the testability of sequential circuits by repositioning registers. A novel retiming…
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Highly Cited
1990
Highly Cited
1990
An optimization based approach to the partial scan design problem
V. Chickermane
,
J. Patel
Proceedings. International Test Conference
1990
Corpus ID: 206676543
The problem of selecting flip-flops for inclusion into a partial scan path is formulated as an optimization problem. Scan flip…
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Highly Cited
1989
Highly Cited
1989
A synthesis and optimization procedure for fully and easily testable sequential machines
S. Devadas
,
Hi-Keung Tony Ma
,
A. Newton
,
A. Sangiovanni-Vincentelli
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1989
Corpus ID: 8016006
The authors outline a synthesis procedure which beginning from a state transition graph (STG) description of a sequential machine…
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Highly Cited
1987
Highly Cited
1987
Designing CMOS Circuits for Switch-Level Testability
Dick L. Liu
,
E. McCluskey
IEEE Design & Test of Computers
1987
Corpus ID: 16747660
Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level…
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Highly Cited
1981
Highly Cited
1981
Node-fault diagnosis and a design of testability
Huang Zheng
,
Raymond Liu
,
Chi-Cheng Steve Lin
20th IEEE Conference on Decision and Control…
1981
Corpus ID: 21169002
A concept of k-node-fault testability is introduced. A sufficient and almost necessary condition for testability as well as the…
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