Signal edge

Known as: Rising edge, Falling edge, Clock-edge 
In electronics, a signal edge is a transition in a digital signal either from low to high (0 to 1) or from high to low (1 to 0). It is called an… (More)
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Topic mentions per year

Topic mentions per year

1963-2017
0204019632017

Papers overview

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2016
2016
A multiplying delay-locked loop (MDLL) is an attractive architecture for a low-jitter clock generator, as it does not suffer much… (More)
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2011
2011
This paper presents a method for recognizing recipe ingredients based on the load on a chopping board when ingredients are cut… (More)
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2010
2010
Surface discharges along oil-immersed solids used as insulators and supports in high-voltage pulsed-power equipment can lead to… (More)
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2008
2008
[1] We present new observational data on small-angle light scattering properties of natural, random shaped particles, as… (More)
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2007
2007
A clock generator fabricated in 90nm CMOS occupies 300times128mum2 die area and dissipates 40mW at 1.2V. An interleaved clock… (More)
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2002
2002
This paper discusses the semantics of the prialt construct in HandelC[1]. The language is essentially a static subset of C… (More)
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2002
2002
We present a technique for rapidly generating highlights of sports videos using temporal patterns of motion activity extracted in… (More)
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2000
2000
An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the… (More)
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Highly Cited
1999
Highly Cited
1999
Characteristics of various CMOS and NMOS circuit techniques are described, along with the shortcomings of each. Then a new… (More)
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1987
1987
The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage… (More)
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