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Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement
TLDR
MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. Expand
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Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained withExpand
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Sub 50-nm FinFET: PMOS
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOSExpand
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An effective gate resistance model for CMOS RF and noise modeling
A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performanceExpand
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An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique
In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.0l fF or 10 aF sensitivity is presented. This on-chip technique is based upon an efficientExpand
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A folded-channel MOSFET for deep-sub-tenth micron era
Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planarExpand
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Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric
We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectricExpand
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Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOIExpand
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A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation
A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gateExpand
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Lucky-electron model of channel hot-electron injection in MOSFET'S
The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature asExpand
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