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- Publications
- Influence
Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement
- Chenming Hu, Simon C. Tam, Fu-Chieh Hsu, Ping-Keung Ko, Tung-Yi Chan, K. Terrill
- Materials Science
- IEEE Journal of Solid-State Circuits
- 1985
TLDR
Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
- Chenming Hu, Simon C. Tam, Fu-Chieh Hsu, Ping-Keung Ko, Tung-Yi Chan, K. Terrill
- Physics
- IEEE Transactions on Electron Devices
- 1985
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with… Expand
Sub 50-nm FinFET: PMOS
- Xuejue Huang, Wen-Chin Lee, +11 authors Chenming Hu
- Materials Science
- International Electron Devices Meeting…
- 5 December 1999
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS… Expand
An effective gate resistance model for CMOS RF and noise modeling
- Xiaodong Jin, Jia-Jiunn Ou, +4 authors Chenming Hu
- Engineering
- International Electron Devices Meeting…
- 1 December 1998
A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance… Expand
An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique
- J.C. Chen, B.W. McGaughy, D. Sylvester, Chenming Hu
- Materials Science, Engineering
- International Electron Devices Meeting. Technical…
- 1 December 1996
In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.0l fF or 10 aF sensitivity is presented. This on-chip technique is based upon an efficient… Expand
A folded-channel MOSFET for deep-sub-tenth micron era
- D. Hisamoto, Wen-Chin Lee, +6 authors Chenming Hu
- Materials Science
- International Electron Devices Meeting…
- 1 December 1998
Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar… Expand
Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric
- Yee Chia Yeo, Qiang Lu, +5 authors T. Ma
- Materials Science
- IEEE Electron Device Letters
- 1 November 2000
We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric… Expand
Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
- Yang-Kyu Choi, K. Asano, +4 authors Chenming Hu
- Materials Science
- IEEE Electron Device Letters
- 1 May 2000
A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI… Expand
A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation
- F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P.K. Ko, Chenming Hu
- Materials Science
- IEEE Electron Device Letters
- 1994
A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate… Expand
Lucky-electron model of channel hot-electron injection in MOSFET'S
- Simon Tam, Ping-Keung Ko, Chenming Hu
- IEEE Transactions on Electron Devices
- 1984
The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as… Expand