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Shift register
Known as:
74HC595
, SR
, Shift registers
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the…
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Related topics
Related topics
50 relations
16550 UART
74181
ADM-3A
ARINC 429
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Broader (1)
Computer memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
Self-Routing Denial-of-Service Resistant Capabilities Using In-packet Bloom Filters
Christian Esteve Rothenberg
,
P. Jokela
,
P. Nikander
,
M. Sarela
,
J. Ylitalo
European Conference on Computer Network Defense
2009
Corpus ID: 15761064
In this paper, we propose and analyze an in-packet Bloom-filter-based source-routing architecture resistant to Distributed Denial…
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2007
2007
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture
H. Noda
,
M. Nakajima
,
+12 authors
Toru Shimizu
IEEE Journal of Solid-State Circuits
2007
Corpus ID: 43656055
This paper describes the design and implementation of the massively parallel processor based on the matrix architecture which is…
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2007
2007
High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function
Máire O’neill
,
C. McIvor
J. VLSI Signal Process.
2007
Corpus ID: 207252595
High-speed and low area hardware architectures of the Whirlpool hash function are presented in this paper. A full Look-up Table…
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2005
2005
Real-Time Software Receiver Tracking of GPS L2 Civilian Signals using a Hardware Simulator
B. Ledvina
,
M. Psiaki
,
S. Powell
,
P. Kintner
2005
Corpus ID: 59484137
A dual-frequency civilian L1/L2 GPS receiver has been tested that runs 12 tracking channels in real time using a software…
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2004
2004
Concatenation of Hamming Codes and Accumulator Codes with High-Order Modulations for High-Speed Decoding
D. Divsalar
,
S. Dolinar
2004
Corpus ID: 234875
We propose a concatenated code structure combined with high-order modulations suitable for implementation with iterative decoders…
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2000
2000
Cryptanalysis of three mutually clock-controlled stop/go shift registers
J. Golic
IEEE Transactions on Information Theory
2000
Corpus ID: 45011839
A binary stream cipher consisting of three short linear-feedback shift registers (LFSRs) of total length 64 that are mutually…
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1994
1994
Amorphous silicon shift register for addressing output drivers
V. D. Costa
,
Russel A. Martin
IEEE J. Solid State Circuits
1994
Corpus ID: 62756228
An amorphous silicon (a-Si) shift register is described. By integrating this shift register design with an array of a-Si drivers…
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1989
1989
A Decomposition Approach for Testing Large Analog Networks*
J. Starzyk
,
H. Dai
1989
Corpus ID: 8460702
This article presents an efficient method for testing large scale analog and mixed mode networks. Test equations are derived lbr…
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1985
1985
On the Linear Complexity of Combined Shift Register Sequences
Lennart Brynielsson
International Conference on the Theory and…
1985
Corpus ID: 10645675
Many proposed keystream generators consist of a number of binary maximum length shift registers combined by a nonlinear binary…
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1965
1965
Minimal Shift-Register Realizations of Sequential Machines
7. Proc.Cambridge
,
Philosoph. Soc
,
+4 authors
M. I. A. J. NICHOLS
IEEE Transactions on Electronic Computers
1965
Corpus ID: 32842709
This paper is concerned with the problem of mechanizing synchronous sequential machines with the least number of shift registers…
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