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Serial computer
A serial computer is typified by bit-serial architecture — i.e., internally operating on one bit or digit for each clock cycle. Machines with serial…
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Related topics
Related topics
23 relations
Arithmetic logic unit
BINAC
Bendix G-15
Bit-level parallelism
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Broader (1)
Classes of computers
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
GPU-ACCELERATED SPH MODEL FOR WATER WAVES AND OTHER FREE SURFACE FLOWS
2011
Corpus ID: 3071327
This paper discusses the meshless numerical method Smoothed Particle Hydrodynamics and its application to water waves and…
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2004
2004
Efficient digit-serial normal basis multipliers over binary extension fields
A. Reyhani-Masoleh
,
M. A. Hasan
TECS
2004
Corpus ID: 12430325
In this article, two digit-serial architectures for normal basis multipliers over (GF(2m)) are presented. These two structures…
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2004
2004
A field programmable bit-serial digital signal processor
S. A. Rahim
,
L. Turner
IEEE International Workshop on System-on-Chip for…
2004
Corpus ID: 18172337
The field programmable digital signal processor (FPDSP) architecture is intended to allow application specific DSP filtering at…
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Highly Cited
2003
Highly Cited
2003
A digital vision chip specialized for high-speed target tracking
T. Komuro
,
I. Ishii
,
M. Ishikawa
,
A. Yoshida
2003
Corpus ID: 305374
This paper describes a new vision chip architecture for high-speed target tracking. The processing speed and the number of pixels…
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1996
1996
A 9 b charge-to-digital converter for integrated image sensors
S. Paul
,
Hae-Seung Lee
IEEE International Solid-State Circuits…
1996
Corpus ID: 321211
An alternative technique for digitizing charge signals, charge-to-digital conversion, is free from many difficulties with…
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1996
1996
The detection of 2D image features using local energy
B. Robbins
1996
Corpus ID: 61013824
Accurate detection and localization of two-dimensional (2D) image features (or `keypoints') is important for vision tasks such as…
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1990
1990
Vestibular Head- Eye Coordination: a Geometrical Sensorimotor Neurocomputer Paradigm#
A. Pellionisz
,
B. Peterson
,
D. Tomko
1990
Corpus ID: 56490956
1989
1989
Bit-serial CORDIC circuits for use in a VLSI silicon compiler
R. Harber
,
Jing Li
,
X. Hu
,
S. Bass
IEEE International Symposium on Circuits and…
1989
Corpus ID: 62393758
The CORDIC algorithm is discussed, and modifications which have been found to make the basic algorithms more flexible are…
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1988
1988
PARALLEL PROCESSING TECHNIQUES FOR FE ANALYSIS: STIFFNESSES, LOADS AND STRESSES EVALUATION
D. Zois
1988
Corpus ID: 17293981
1985
1985
A multi-processor cellular automaton chip
K. Steiglitz
,
Ronald R. Morita
ICASSP '85. IEEE International Conference on…
1985
Corpus ID: 60817379
We describe the design and testing of an 18- processor chip that implements the update rule for a fixed one-dimensional binary…
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