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Serial computer

A serial computer is typified by bit-serial architecture — i.e., internally operating on one bit or digit for each clock cycle. Machines with serial… 
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Related topics

Related topics

23 relations
Arithmetic logic unitBINACBendix G-15Bit-level parallelism

Broader (1)

Classes of computers

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
GPU-ACCELERATED SPH MODEL FOR WATER WAVES AND OTHER FREE SURFACE FLOWS
  • 2011
  • Corpus ID: 3071327
This paper discusses the meshless numerical method Smoothed Particle Hydrodynamics and its application to water waves and… 
2004
2004
Efficient digit-serial normal basis multipliers over binary extension fields
In this article, two digit-serial architectures for normal basis multipliers over (GF(2m)) are presented. These two structures… 
2004
2004
A field programmable bit-serial digital signal processor
The field programmable digital signal processor (FPDSP) architecture is intended to allow application specific DSP filtering at… 
Highly Cited
2003
Highly Cited
2003
A digital vision chip specialized for high-speed target tracking
This paper describes a new vision chip architecture for high-speed target tracking. The processing speed and the number of pixels… 
1996
1996
A 9 b charge-to-digital converter for integrated image sensors
An alternative technique for digitizing charge signals, charge-to-digital conversion, is free from many difficulties with… 
1996
1996
The detection of 2D image features using local energy
Accurate detection and localization of two-dimensional (2D) image features (or `keypoints') is important for vision tasks such as… 
1990
1990
Vestibular Head- Eye Coordination: a Geometrical Sensorimotor Neurocomputer Paradigm#
1989
1989
Bit-serial CORDIC circuits for use in a VLSI silicon compiler
The CORDIC algorithm is discussed, and modifications which have been found to make the basic algorithms more flexible are… 
1988
1988
PARALLEL PROCESSING TECHNIQUES FOR FE ANALYSIS: STIFFNESSES, LOADS AND STRESSES EVALUATION
1985
1985
A multi-processor cellular automaton chip
We describe the design and testing of an 18- processor chip that implements the update rule for a fixed one-dimensional binary… 
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