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Serial computer
A serial computer is typified by bit-serial architecture — i.e., internally operating on one bit or digit for each clock cycle. Machines with serial…
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Related topics
Related topics
23 relations
Arithmetic logic unit
BINAC
Bendix G-15
Bit-level parallelism
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Broader (1)
Classes of computers
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2007
Highly Cited
2007
On Concurrent Detection of Errors in Polynomial Basis Multiplication
S. Bayat-Sarmadi
,
M. Anwar Hasan
IEEE Transactions on Very Large Scale Integration…
2007
Corpus ID: 188493
The detection of errors in arithmetic operations is an important issue. This paper discusses the detection of multiple-bit errors…
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2006
2006
A family of time-staggered schemes for integrating hybrid DPD models for polymers: Algorithms and applications
V. Symeonidis
,
G. Karniadakis
Journal of Computational Physics
2006
Corpus ID: 18221457
Highly Cited
2003
Highly Cited
2003
A digital vision chip specialized for high-speed target tracking
T. Komuro
,
I. Ishii
,
M. Ishikawa
,
A. Yoshida
2003
Corpus ID: 305374
This paper describes a new vision chip architecture for high-speed target tracking. The processing speed and the number of pixels…
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1996
1996
A 9 b charge-to-digital converter for integrated image sensors
S. Paul
,
Hae-Seung Lee
IEEE International Solid-State Circuits…
1996
Corpus ID: 321211
An alternative technique for digitizing charge signals, charge-to-digital conversion, is free from many difficulties with…
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1996
1996
The detection of 2D image features using local energy
B. Robbins
1996
Corpus ID: 61013824
Accurate detection and localization of two-dimensional (2D) image features (or `keypoints') is important for vision tasks such as…
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1990
1990
A bit-serial VLSI array processing chip for image processing
R. A. Heaton
,
D. W. Blevins
,
E. Davis
1990
Corpus ID: 62529684
An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16…
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1990
1990
Vestibular Head- Eye Coordination: a Geometrical Sensorimotor Neurocomputer Paradigm#
A. Pellionisz
,
B. Peterson
,
D. Tomko
1990
Corpus ID: 56490956
1988
1988
PARALLEL PROCESSING TECHNIQUES FOR FE ANALYSIS: STIFFNESSES, LOADS AND STRESSES EVALUATION
D. Zois
1988
Corpus ID: 17293981
1985
1985
A multi-processor cellular automaton chip
K. Steiglitz
,
Ronald R. Morita
ICASSP '85. IEEE International Conference on…
1985
Corpus ID: 60817379
We describe the design and testing of an 18- processor chip that implements the update rule for a fixed one-dimensional binary…
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Review
1977
Review
1977
Associative Processor Architecture—a Survey
S. Yau
,
H. S. Fung
CSUR
1977
Corpus ID: 1019634
A survey of the architecture of various associative processors is presented with emphasis on their characteristics…
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