Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 233,247,800 papers from all fields of science
Search
Sign In
Create Free Account
SPECint
Known as:
CINT2000
SPECint is a computer benchmark specification for CPU integer processing power. It is maintained by the Standard Performance Evaluation Corporation…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
21 relations
Benchmark (computing)
Central processing unit
Compiler
Dhrystone
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
CASM: Implementing an Abstract State Machine based Programming Language
Roland Lezuo
,
Gergö Barany
,
A. Krall
Software Engineering
2013
Corpus ID: 16965697
In this paper we present CASM, a general purpose programming language based on abstract state machines (ASMs). We describe the…
Expand
2007
2007
Asymmetrically Banked Value-Aware Register Files
Shuai Wang
,
Hongyan Yang
,
Jie S. Hu
,
Sotirios G. Ziavras
IEEE Computer Society Annual Symposium on VLSI
2007
Corpus ID: 7383154
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances…
Expand
2006
2006
Low-Power, High-Performance Architecture of the PWRficient Processor Family
Tse-Yu Yeh
IEEE Micro
2006
Corpus ID: 12138555
The dual-core PA6T-1682M system on chip (SoC) is the first design in the PWRficient family of high-performance, low-power…
Expand
2005
2005
A Systematic Approach to Delivering Instruction-Level Parallelism in EPIC Systems
J. Sias
2005
Corpus ID: 58970399
Computer systems designed under the explicitly parallel instruction computing (EPIC) paradigm rely extensively on compiler…
Expand
2004
2004
Rapid Development of a Flexible Validated Processor Model
D. Penry
,
David I. August
,
Manish Vachharajani
2004
Corpus ID: 445362
validated models. Unfortunately, they only present anecdotal and secondary evidence to support their claims. In this paper, we…
Expand
2004
2004
Reducing program image size by extracting frozen code and data
D. Citron
,
Gadi Haber
,
R. Levin
International Conference on Embedded Software
2004
Corpus ID: 15132165
Constraints on the memory size of embedded systems require reducing the image size of executing programs. Common techniques…
Expand
2003
2003
Managing Leakage Energy in Cache Hierarchies
Lin Li
,
I. Kadayif
,
+4 authors
A. Sivasubramaniam
J. Instr. Level Parallelism
2003
Corpus ID: 17282822
Energy management is important for a spectrum of systems ranging from high-performance architectures to low-end mobile and…
Expand
2002
2002
Simulating L3 caches in real time using hardware accelerated cache simulation (HACS): a case study with SPECint 2000
Myles Watson
,
J. Flanagan
Symposium on Computer Architecture and High…
2002
Corpus ID: 14792542
Trace-driven simulation is a commonly used tool to evaluate memory-hierarchy designs. Unfortunately, trace collection is very…
Expand
2002
2002
Benchmarking Web Server Architectures : A Simulation Study on Micro Performance
Haiyong Xie
,
L. Bhuyan
,
Yeim-Kuan Chang
2002
Corpus ID: 14433644
As Internet expands, the number of application servers, especially Web servers, has been increasing exponentially. To improve the…
Expand
1996
1996
High-performance image processing using special-purpose cpu instructions: the ultrasparc visual inst
D. Rice
1996
Corpus ID: 11717058
The UltraSPARC-I processor implements, in addition to the SPARC v9 instruction set, a set of new instructions that accelerate…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE