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Phase-locked loop

Known as: Digital phase-locked loop, Phase-locked synchronization circuit, Phase-Lock Loop 
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2006
2006
The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations… 
Highly Cited
2002
Highly Cited
2002
This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter… 
Highly Cited
2000
Highly Cited
2000
An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive… 
1994
1994
The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 /spl mu/m, 20 GHz BiCMOS technology is described. The… 
Highly Cited
1992
Highly Cited
1992
The recently developed technique of time‐resolved spectroscopy with phase‐locked optical pulse pairs is further explored with… 
Highly Cited
1989
Highly Cited
1989
The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage… 
Highly Cited
1989
Highly Cited
1989
A second-order digital phase-locked loop may exhibit unusual behavior for some parameters due to a fractal boundary between the… 
Highly Cited
1977
Highly Cited
1977
A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged… 
1977
1977
A heterodyne phase locked loop has been studied in detail with particular emphasis on the spurious mode of locking called False… 
1975
1975
This paper describes a motor control circuit for a dc motor using phase-locked loop techniques. The purpose of such a control…