Skip to search formSkip to main contentSkip to account menu

PBIST

Programmable Built-In Self-Test (PBIST) is a memory DFT feature that incorporates all the required test systems into the chip itself. The test… 
Wikipedia (opens in a new tab)

Related topics

Related topics

4 relations
Built-in self-testJTAGLogic built-in self-test

Broader (1)

Electronic design automation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A programmable BIST with macro and micro codes for embedded SRAMs
This paper presents a programmable built-in self-test (PBIST) methodology for embedded SRAMs. The BIST logic adapts the test… 
2011
2011
Leakage Current Optimization in Sleepy SRAM at 45nm Technology
Every new generation of process technology at Intel is developed and certified using an SRAM-based “X-chip.”X6 is the technology… 
2008
2008
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips
Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include… 
2008
2008
45nm SRAM Technology Development and Technology Lead Vehicle
Every new generation of process technology at Intel is developed and certified using an SRAM-based “X-chip.” X6 is the technology… 
2000
2000
7-4 A 16GB/s, 0.18p.m Cache Tile for Integrated L2 Caches from 256KB to 2MB.
A modular 256KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18pm Intel… 
2000
2000
A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB
A modular 256 KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18 /spl mu… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)