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JTAG
Known as:
1149.1
, IEEE 1149
, Wiggler (JTAG)
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The Joint Test Action Group (JTAG) is an electronics industry association formed in 1985 for developing a method of verifying designs and testing…
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Related topics
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50 relations
ARM architecture
ARM7
AVR Butterfly
AVR32
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
B. Vermeulen
,
K. Goossens
,
Siddharth Umrani
ACM/IEEE International Symposium on Networks-on…
2008
Corpus ID: 6593933
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a…
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2002
2002
IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips
B. Vermeulen
,
T. Waayers
,
S. Bakker
Proceedings. International Test Conference
2002
Corpus ID: 26512163
To enable the efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be…
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Highly Cited
2001
Highly Cited
2001
Enhanced Reduced Pin-Count Test for Full-Scan Design
H. Vranken
,
T. Waayers
,
H. Fleury
,
David Lelouvier
Proceedings International Test Conference (Cat…
2001
Corpus ID: 26633590
This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for…
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1999
1999
An embedded technique for at-speed interconnect testing
B. Nadeau-Dostie
,
J. Cote
,
H. Hulvershorn
,
S. Pateras
International Test Conference . Proceedings (IEEE…
1999
Corpus ID: 31363593
A new embedded test technique which provides full at-speed testing of board level interconnect is described. The proposed…
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Highly Cited
1998
Highly Cited
1998
Hierarchical test access architecture for embedded cores in an integrated circuit
D. Bhattacharya
Proceedings of the ... IEEE VLSI Test Symposium
1998
Corpus ID: 42014856
The rapid emergence of reusable core-based designs, in the last few years, poses new challenges to the IEEE test access standard…
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1997
1997
A BIST and Boundary-Scan Economics Framework
J. M. Miranda
IEEE Design & Test of Computers
1997
Corpus ID: 8344309
IC level built-in self-test and IEEE 1149.1 boundary-scan architecture offer potential benefits at all phases of a product's life…
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Highly Cited
1993
Highly Cited
1993
Structure and metrology for an analog testability bus
K. Parker
,
J. McDermid
,
S. Oresjo
International Test Conference
1993
Corpus ID: 41323958
This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4…
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1992
1992
A Proposed Method of Accessing 1149.1 in a Backplane Environment
L. Whetsel
Proceedings International Test Conference
1992
Corpus ID: 34757944
1991
1991
An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes
D. Bhavsar
, Proceedings. International Test Conference
1991
Corpus ID: 43659899
Tbts paper presents an arclcecrute for niakms the EEE Standard 1139.1 lest acces port did dl it? major provisions available on a…
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Highly Cited
1990
Highly Cited
1990
A language for describing boundary scan devices
K. Parker
,
S. Oresjo
Proceedings. International Test Conference
1990
Corpus ID: 38829022
Boundary scan (IEEE Standard 1149.1-1990) technology is beginning to be embraced in chip and board designs. One key need is a way…
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