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JTAG
Known as:
1149.1
, IEEE 1149
, Wiggler (JTAG)
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The Joint Test Action Group (JTAG) is an electronics industry association formed in 1985 for developing a method of verifying designs and testing…
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Related topics
Related topics
50 relations
ARM architecture
ARM7
AVR Butterfly
AVR32
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Application of the Internet of Things Technology in Smart Grid
Cui Dong
,
Jianli Zhou
,
Moqi Wang
2015
Corpus ID: 58890372
According to the application of IOT (Internet of things) in smart grid, intelligent network node of the IOT based on ARM, GSM…
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2002
2002
Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost
S. Sunter
,
B. Nadeau-Dostie
Proceedings. International Test Conference
2002
Corpus ID: 30888198
Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed…
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2001
2001
Use of BIST in Sun Fire/sup TM/ servers
J. Braden
,
Qing Lin
,
Brian Smith
Proceedings International Test Conference (Cat…
2001
Corpus ID: 29896585
The latest UltraSPARC/sup TM/ III generation of servers from Sun Microsystems makes extensive use of BIST and other DFT…
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2000
2000
Power pin testing: making the test coverage complete
F. de Jong
,
Ben Kup
,
Rodger Schuttert
Proceedings International Test Conference (IEEE…
2000
Corpus ID: 6030716
Most modern ICs have multiple power and ground pins. It becomes necessary that all these pins are indeed connected to the board…
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1997
1997
A BIST and Boundary-Scan Economics Framework
J. M. Miranda
IEEE Design & Test of Computers
1997
Corpus ID: 8344309
IC level built-in self-test and IEEE 1149.1 boundary-scan architecture offer potential benefits at all phases of a product's life…
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1997
1997
DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1
Prashant Goteti
,
Giri Devarayanadurg
,
M. Soma
IEEE Custom Integrated Circuits Conference
1997
Corpus ID: 62762088
In this work we present a DFT strategy to test embedded Charge-Pump Phase Locked Loops (CP-PLL) in systems incorporating boundary…
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1995
1995
Clock controller design in SuperSPARC II microprocessor
Hong Hao
,
K. Bhabuthmal
Proceedings of ICCD '95 International Conference…
1995
Corpus ID: 35782346
This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip…
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1995
1995
Integration of IEEE STD.11149.1 and mixed-signal test architectures
David J. Cheek
,
R. Dandapani
International Test Conference
1995
Corpus ID: 42099832
It is shown that the TMS pin of IEEE Std. 1149.1 can also be-used for providing stimulus during analog measurements using the…
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1993
1993
Towards a test standard for board and system level mixed-signal interconnects
Carl W. Thatcher
,
R. Tulloss
International Test Conference
1993
Corpus ID: 37814628
This paper describes basic requirements for a standard bus for testing analog interconnects. The viewpoint is that of prospective…
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1993
1993
Hierarchically accessing 1149.1 applications in a system environment
L. Whetsel
International Test Conference
1993
Corpus ID: 27578453
This paper presents a novel connection method that enables in 1149.1 test bus controller to hierarchically access and test 1149.1…
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