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JTAG
Known as:
1149.1
, IEEE 1149
, Wiggler (JTAG)
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The Joint Test Action Group (JTAG) is an electronics industry association formed in 1985 for developing a method of verifying designs and testing…
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ARM architecture
ARM7
AVR Butterfly
AVR32
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2003
Review
2003
An improved test control architecture and test control expansion for core-based system chips
T. Waayers
International Test Conference, . Proceedings. ITC…
2003
Corpus ID: 17970144
Abstract This paper presents improvement of a core-based chip™s test control architecture that uses Std IEEE 1149.1 TAP to access…
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2002
2002
Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost
S. Sunter
,
B. Nadeau-Dostie
Proceedings. International Test Conference
2002
Corpus ID: 30888198
Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed…
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2000
2000
Power pin testing: making the test coverage complete
F. Jong
,
B. Kup
,
R. Schuttert
Proceedings International Test Conference (IEEE…
2000
Corpus ID: 6030716
Most modern ICs have multiple power and ground pins. It becomes necessary that all these pins are indeed connected to the board…
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1998
1998
An extensible, low cost rapid prototyping environment based on a reconfigurable set of FPGAs
K. Adaos
,
G. Alexiou
,
N. Kanopoulos
Proceedings. Ninth International Workshop on…
1998
Corpus ID: 4789214
Presents the architecture of a system for the rapid prototyping of digital circuits that is based an the Altera FLEX8000…
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1997
1997
A BIST and Boundary-Scan Economics Framework
J. M. Miranda
IEEE Design & Test of Computers
1997
Corpus ID: 8344309
IC level built-in self-test and IEEE 1149.1 boundary-scan architecture offer potential benefits at all phases of a product's life…
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1995
1995
Clock controller design in SuperSPARC II microprocessor
Hong Hao
,
K. Bhabuthmal
Proceedings of ICCD '95 International Conference…
1995
Corpus ID: 35782346
This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip…
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1994
1994
Boundary-scan: beyond production test
R.M. Sedmark
Proceedings of the ... IEEE VLSI Test Symposium
1994
Corpus ID: 206855404
The use of boundary-scan, as specified in IEEE 1149.1-1990, has always been considered a source of major benefits for the…
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1993
1993
Towards a test standard for board and system level mixed-signal interconnects
Carl W. Thatcher
,
R. Tulloss
International Test Conference
1993
Corpus ID: 37814628
This paper describes basic requirements for a standard bus for testing analog interconnects. The viewpoint is that of prospective…
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1993
1993
Hierarchically accessing 1149.1 applications in a system environment
L. Whetsel
International Test Conference
1993
Corpus ID: 27578453
This paper presents a novel connection method that enables in 1149.1 test bus controller to hierarchically access and test 1149.1…
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1991
1991
Testing interconnections to static RAMs
D. Bhavsar
IEEE Design & Test of Computers
1991
Corpus ID: 25277193
A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE…
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