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Overclocking
Known as:
Over clocking
, O/c
, Clock locking
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Overclocking is the configuration of a computer hardware component to operate at a faster rate than was certified by the original manufacturer…
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Related topics
Related topics
50 relations
3DMark
AMD 690 chipset series
Accelerated Graphics Port
Athlon
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Broader (1)
Clock signal
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
DyRACT: A partial reconfiguration enabled accelerator and test platform
Kizheppatt Vipin
,
Suhaib A. Fahmy
International Conference on Field-Programmable…
2014
Corpus ID: 206657317
Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that…
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Highly Cited
2012
Highly Cited
2012
Formation of anthropogenic secondary organic aerosol (SOA) and its influence on biogenic SOA properties
E. Emanuelsson
,
M. Hallquist
,
+11 authors
T. Mentel
2012
Corpus ID: 3860413
Abstract. Secondary organic aerosol (SOA) formation from mixed anthropogenic and biogenic precursors has been studied exposing…
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Highly Cited
2011
Highly Cited
2011
MACACO: Modeling and analysis of circuits for approximate computing
Rangharajan Venkatesan
,
A. Agarwal
,
K. Roy
,
A. Raghunathan
IEEE/ACM International Conference on Computer…
2011
Corpus ID: 1343003
Approximate computing, which refers to a class of techniques that relax the requirement of exact equivalence between the…
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Highly Cited
2011
Highly Cited
2011
High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro
Simen Gimle Hansen
,
Dirk Koch
,
J. Tørresen
IEEE International Symposium on Parallel…
2011
Corpus ID: 15861851
Achieving high speed run-time reconfiguration is important for the adaptation of partial reconfiguration in many applications…
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Highly Cited
2011
Highly Cited
2011
Practical performance prediction under Dynamic Voltage Frequency Scaling
B. Rountree
,
D. Lowenthal
,
M. Schulz
,
B. Supinski
International Green Computing Conference and…
2011
Corpus ID: 7184912
Predicting performance under Dynamic Voltage Frequency Scaling (DVFS) remains an open problem. Current best practice explores…
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Review
2009
Review
2009
Hard Data on Soft Errors: A Large-Scale Assessment of Real-World Error Rates in GPGPU
I. Haque
,
V. Pande
10th IEEE/ACM International Conference on Cluster…
2009
Corpus ID: 10723933
Graphics processing units (GPUs) are gaining widespread use in high-performance computing because of their performance advantages…
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Highly Cited
2009
Highly Cited
2009
Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs
N. D. Avirneni
,
Viswanathan Subramanian
,
Arun Kumar Somani
IEEE transactions on computers
2009
Corpus ID: 7187426
The threat of soft error induced system failure in computing systems has become more prominent, as we adopt ultradeep submicron…
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Review
2006
Review
2006
Compact Stellar X-Ray Sources: Black hole binaries
J. McClintock
,
R. Remillard
2006
Corpus ID: 8975056
4.1.1 Scope of this review We focus on 18 black holes with measured masses that are located in X–ray binary systems. These black…
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Highly Cited
2005
Highly Cited
2005
Pioneer: verifying code integrity and enforcing untampered code execution on legacy systems
Arvind Seshadri
,
M. Luk
,
A. Perrig
,
L. V. Doorn
,
P. Khosla
Symposium on Operating Systems Principles
2005
Corpus ID: 9960430
We propose a primitive, called Pioneer, as a first step towards verifiable code execution on untrusted legacy hosts. Pioneer does…
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Highly Cited
1994
Highly Cited
1994
A Wide-Bandwidth Low-Voltage Pll for Powerpc Microprocessors
J. Alvarez
,
H. Sanchez
,
G. Gerosa
,
C. Hanke
,
R. Countryman
,
S. Thadasina
Proceedings of IEEE Symposium on VLSI Circuits
1994
Corpus ID: 57681852
A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 /spl mu/m CMOS technology is described. The PLL supports…
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