Rajesh Velegalati

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Current techniques to implement Dynamic Differential Logic (DDL), a countermeasure against Differential Power Analysis (DPA) on Field Programmable Gate Arrays (FPGAs) lead to an increase in area consumption of up to factor 11. In this paper we introduce Partial DDL, a technique in which DDL is applied only to a part of the cryptographic hardware(More)
Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential(More)
Implementations of mathematically secure cryptographic algorithms leak information through side channels during run time. Differential Power Analysis (DPA) attacks exploit power leakage to obtain the secret information. Dynamic and Differential Logic (DDL), one of the popular countermeasures against DPA attacks, tries to achieve constant power consumption(More)
Recent advances in Field Programmable Gate Array (FPGA) technology are bound to make FPGAs a popular platform for battery powered devices. Many applications of such devices are mission critical and require the use of cryptographic algorithms to provide the desired security. However, Differential Power Analysis (DPA) attacks pose a sever threat against(More)
Block RAMs (BRAMs) are commonly used by implementations of cryptographic algorithms on Field Programmable Gate Arrays (FPGAs). Unfortunately, any hardware implementation of a cryptographic function is susceptible to differential power analysis (DPA) attacks unless it is protected. Dynamic and Differential Logic (DDL), a constant power consumption logic(More)
Side-channel analysis attacks pose a growing threat to implementations of cryptographic algorithms implemented in software as well as in hardware. Current standard side-channel evaluation boards with Field Programmable Gate Arrays (FPGAs), that allow for exploring the vulnerability of cryptographic implementations on FPGAs, are expensive and available only(More)
Glitches are the spurious signal transitions, which occur due to unbalanced path delays at the inputs of a gate. Presence of glitches in a digital system increases the number of signal transitions, thereby increasing the dynamic power consumption of the system. Consequently, overall power consumption, a major design criteria of a digital system, is(More)
Benchmarking of digital designs targeting FPGAs is a time intensive and challenging process. Benchmarking results depend on a myriad of variables beyond the properties inherent to the designs being evaluated, encompassing the tools, tool options, FPGA families, and languages used. In this paper we will be discussing enhancements made to the ATHENa(More)
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