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Operand isolation

In electronic low power digital synchronous circuit design, operand isolation is a technique for minimizing the energy overhead associated with… 
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Related topics

Related topics

4 relations
AND gateClock gatingPipeline (computing)Synchronous circuit

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems
The drastic increase in Internet usage demands the need for processing data in real time with higher efficiency than ever before… 
2011
2011
EVALUATION OF LOW POWER DESIGN TECHNIQUES ON AN MPEG 2 VIDEO DECODER PLATFORM
  • Y. Ju
  • 2011
  • Corpus ID: 18889674
In this paper, we discuss the design and evaluation of low-power optimization techniques on an industrialstrength MPEG-2 SoC… 
2011
2011
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays
The presented evaluation framework allows extremely fast but still accurate power, area, and latency characterization of… 
2011
2011
Design of a Floating-point Fixed-point Fused FALU
ALU is the key functional unit of modern CPU and DSP.This paper introduced a Floating-point Fixed-point fused FALU,Through… 
2010
2010
System level simulation guided approach to improve the efficacy of clock-gating
Clock-gating is a well known technique to reduce dynamic power consumption of a hardware design. In any clock-gating based power… 
2009
2009
LOW-POWER DESIGN OF DIGITAL SIGNAL PROCESSING BLOCK FOR INTEGRATED POWER METER
– The paper considers the architecture and low power design aspects of the digital signal processing block (DSP) embedded into a… 
2007
2007
Low Power Circuit Architecture of AES Crypto Module for Wireless Sensor Network
— Recently, much research has been conducted for security for wireless sensor networks and ubiquitous computing. Security issues… 
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