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Pipeline (computing)
Known as:
Pipeline
, Pipeline (computer)
, Pipe
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In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one. The…
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50 relations
256-bit
AIPS
AMULET microprocessor
ARM architecture
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency
R. Taft
,
P. Francese
,
+6 authors
Andrew Glenny
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 42107293
An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to…
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Highly Cited
2008
Highly Cited
2008
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
I. Ahmed
,
D. Johns
IEEE Journal of Solid-State Circuits
2008
Corpus ID: 6288179
A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented…
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Highly Cited
2007
Highly Cited
2007
A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction
Jia-Ching Wang
,
Jhing-Fa Wang
,
J. Yang
,
Jang-Ting Chen
IEEE transactions on circuits and systems for…
2007
Corpus ID: 10884869
In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular…
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Highly Cited
2004
Highly Cited
2004
A power-aware scalable pipelined Booth multiplier
Hanho Lee
IEEE International SOC Conference, . Proceedings.
2004
Corpus ID: 3060399
Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios…
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Highly Cited
1998
Highly Cited
1998
A low-power IDCT macrocell for MPEG2 MP@ML exploiting data distribution properties for minimal activity
T. Xanthopoulos
,
A. Chandrakasan
Symposium on VLSI Circuits. Digest of Technical…
1998
Corpus ID: 14383164
This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy…
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Highly Cited
1997
Highly Cited
1997
Renumbering strategies for unstructured-grid solvers operating on shared-memory, cache-based parallel machines
R. Loehner
1997
Corpus ID: 61484452
Highly Cited
1996
Highly Cited
1996
Module assignment for low power
Massoud Pedram
,
Jui-Ming Chang
Proceedings EURO-DAC '96. European Design…
1996
Corpus ID: 862685
We investigate the problem of minimizing the total power consumption during the binding of operations to functional units in a…
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Highly Cited
1991
Highly Cited
1991
Pipelined Communications in Optically Interconnected Arrays
Zicheng Guo
,
R. Melhem
,
R. W. Hall
,
D. Chiarulli
,
S. Levitan
J. Parallel Distributed Comput.
1991
Corpus ID: 15804060
Highly Cited
1983
Highly Cited
1983
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
Dhruva Nath
,
S. Maheshwari
,
P. Bhatt
IEEE transactions on computers
1983
Corpus ID: 22667234
In this paper we describe two interconnection networks for parallel processing, namely the orthogonal trees network and the…
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Highly Cited
1981
Highly Cited
1981
Computer Architectures for Pictorial Information Systems
P. Danielsson
,
S. Levialdi
Computer
1981
Corpus ID: 14554894
In the international search for the optimal image processing computer architecture, image parallelism is the key to cost…
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