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Pipeline (computing)
Known as:
Pipeline
, Pipeline (computer)
, Pipe
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In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one. The…
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Related topics
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50 relations
256-bit
AIPS
AMULET microprocessor
ARM architecture
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Papers overview
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Highly Cited
2010
Highly Cited
2010
Design of High-speed Modified Booth Multipliers Operating at GHz Ranges
Soojin Kim
,
Kyeongsoon Cho
2010
Corpus ID: 17071803
— This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are…
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Highly Cited
2001
Highly Cited
2001
A Pipeline Chip for Quasi Arithmetic Coding
Y. Wiseman
2001
Corpus ID: 19019091
SUMMARY A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is…
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Highly Cited
1998
Highly Cited
1998
A low-power IDCT macrocell for MPEG2 MP@ML exploiting data distribution properties for minimal activity
T. Xanthopoulos
,
A. Chandrakasan
Symposium on VLSI Circuits. Digest of Technical…
1998
Corpus ID: 14383164
This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy…
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Highly Cited
1997
Highly Cited
1997
Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN
Naresh R Shanbhag
,
M. Goel
IEEE Transactions on Signal Processing
1997
Corpus ID: 224823
We present low-power and high-speed algorithms and architectures for complex adaptive filters. These architectures have been…
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Highly Cited
1996
Highly Cited
1996
Module assignment for low power
Massoud Pedram
,
Jui-Ming Chang
Proceedings EURO-DAC '96. European Design…
1996
Corpus ID: 862685
We investigate the problem of minimizing the total power consumption during the binding of operations to functional units in a…
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1995
1995
Internal architecture of Alpha 21164 microprocessor
P. Bannon
,
J. Keller
Digest of Papers. COMPCON'95. Technologies for…
1995
Corpus ID: 206567870
The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This…
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Highly Cited
1992
Highly Cited
1992
Predicting system-level area and delay for pipelined and nonpipelined designs
R. Jain
,
A. C. Parker
,
N. Park
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1992
Corpus ID: 206439685
The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality…
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1984
1984
Acoustooptic linear algebra processors: Architectures, algorithms, and applications
D. Casasent
Proceedings of the IEEE
1984
Corpus ID: 25525321
Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel…
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Highly Cited
1983
Highly Cited
1983
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
Dhruva Nath
,
S. Maheshwari
,
P. Bhatt
IEEE transactions on computers
1983
Corpus ID: 22667234
In this paper we describe two interconnection networks for parallel processing, namely the orthogonal trees network and the…
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Highly Cited
1981
Highly Cited
1981
A Two-Level Pipelined Systolic Array for Convolutions
H. T. Kung
,
Lawrence M. Ruane
,
David W. L. Yen
1981
Corpus ID: 59827955
Pipelining computations over a large array of cells has been an important feature of systolic arrays. To achieve even higher…
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