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Multiplier Device Component
Known as:
Multiplier
A device designed to take an input and increase some characteristic of it.
National Institutes of Health
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Medical Device Component or Accessory
Papers overview
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2018
2018
On Lagrange Multiplier Tests in Multidimensional Item Response Theory: Information Matrices and Model Misspecification
Carl F. Falk
,
S. Monroe
Educational and Psychological Measurement
2018
Corpus ID: 52092405
Lagrange multiplier (LM) or score tests have seen renewed interest for the purpose of diagnosing misspecification in item…
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2015
2015
A 0.0045- $\hbox{mm}^{2}$ 32.4- $\mu\hbox{W} $ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation
Zushu Yan
,
Wei Wang
,
Pui-in Mak
,
M. Law
,
R. Martins
IEEE Transactions on Circuits and Systems - II…
2015
Corpus ID: 14451610
This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact…
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2012
2012
Design of single neuron on FPGA
K. Mohamad
,
M. F. O. Mahmud
,
F. H. Adnan
,
W. Abdullah
IEEE Symposium on Humanities, Science and…
2012
Corpus ID: 34381558
This paper presents a digital design of neuron architecture on field-programmable gate array (FPGA). The objective of this…
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2010
2010
ROBUST CRITICAL VALUES FOR THE JARQUE-BERA TEST FOR NORMALITY
P. Mantalos
2010
Corpus ID: 13032418
We introduce the “sample” technique to generate robust critical values for the Jarque and Bera (JB) Lagrangian Multiplier (LM…
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2010
2010
A Floating Point Multiplier based FPGA Synthesis for Neural Networks Enhancement
F. Benrekia
,
M. Attari
2010
Corpus ID: 14802958
FPGA (Field Programmable Gate Array) implementation of Artificial Neural Networks (ANNs) calls for multipliers of various word…
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1998
1998
A Monte Carlo Investigation of Methods for Controlling Type I Errors with Specification Searches in Structural Equation Modeling.
S. Green
,
M. Thompson
,
M. Babyak
Multivariate Behavioral Research
1998
Corpus ID: 25574055
A standard strategy in structural equation modeling is to conduct multiple Lagrange multiplier (LM) tests after rejection of an…
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1989
1989
A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture
K. Aono
,
M. Toyokura
,
T. Araki
Proceedings of the IEEE Custom Integrated…
1989
Corpus ID: 62586510
A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable…
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1988
1988
Generation of high speed CMOS multiplier-accumulators
K. F. Pang
,
H.-W. Soong
,
R. Sexton
,
P. Ang
Conference on Advanced Research in VLSI
1988
Corpus ID: 61166073
The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace…
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1985
1985
Image processing address generator chip
J. Eldon
,
Z. Stroll
,
E. Swartzlander
ICASSP '85. IEEE International Conference on…
1985
Corpus ID: 61776808
Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requires large RAMs, fast multiplier…
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1979
1979
LSI's for digital signal processing
N. Ohwada
,
T. Kimura
,
M. Doken
IEEE Transactions on Electron Devices
1979
Corpus ID: 21029511
This paper describes high-performance CMOS LSI's for digital signal-processing (DSP) technology, such as digital filter, fast…
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