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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TLDR
A 1.2 V 10-bit 100 MS/s Successive Approximation ADC achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Expand
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Transceiver architecture selection: Review, state-of-the-art survey and case study
© P H O T O D IS C A N D C R E A TA S Feature
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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
TLDR
An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. Expand
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Miniaturized microstrip lowpass filter with wide stopband using double equilateral U-shaped defected ground structure
A compact double equilateral U-shaped defected ground structure (DGS) unit is proposed. In contrast to a single finite attenuation pole characteristic offered by the conventional dumbbell DGS, theExpand
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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
TLDR
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. Expand
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A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation
TLDR
The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. Expand
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A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW
TLDR
A 0.016-mm 144W three-stage amplifier capable of driving 1-to-15-nF capacitive load with large-and-wide drivability . Expand
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An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator
TLDR
This paper presents an analog-assisted (AA) output-capacitor-free digital low-dropout (D-LDO) regulator with tri-loop control. Expand
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15-nW Biopotential LPFs in 0.35- $\mu{\rm m}$ CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation
TLDR
This paper presents an in-depth treatment of SSF Biquad in the nW-power regime, analyzing its power and area tradeoffs with gain, linearity and noise. Expand
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