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Memory bus
Known as:
RAM bus
The memory bus is the computer bus which connects the main memory to the memory controller in computer systems. Originally, general-purpose buses…
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AMD Radeon 400 series
ATI Radeon R200 series
Address bus
Alpha 21064
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Motherboard
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data
Vivek Seshadri
,
Yoongu Kim
,
+8 authors
T. Mowry
2013
Corpus ID: 3065319
Many programs initialize or copy large amounts of memory data. Initialization and copying are forms of memory operations that do…
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2013
2013
Graphics processing unit acceleration of the red/black SOR method
E. Konstantinidis
,
Y. Cotronis
Concurrency and Computation
2013
Corpus ID: 30204201
This work presents our strategy, applied optimizations and results in our effort to exploit the computational capabilities of…
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2010
2010
Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems
Björn Andersson
,
A. Easwaran
,
Jinkyu Lee
SIGBED
2010
Corpus ID: 2138570
Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a…
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2009
2009
Characterizing Application Performance Sensitivity to R esource Contention in Multicore Architectures
Haoqiang Jin
,
R. Hood
,
+5 authors
P. Mehrotra
2009
Corpus ID: 6753818
Contention for shared resources in the memory hierarchy can have a profound effect on the performance of applications running on…
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2007
2007
Parametric Performance Contracts for Software Components with Concurrent Behaviour
J. Happe
,
Heiko Koziolek
,
Ralf H. Reussner
International Workshop on Formal Aspects of…
2007
Corpus ID: 12801126
2006
2006
Loosely Coupled TCP Acceleration Architecture
Lea Shalev
,
Vadim Makhervaks
,
+4 authors
Ilan Shimony
IEEE Symposium on High-Performance Interconnects
2006
Corpus ID: 8134345
We present a novel approach for scalable network acceleration. The architecture uses limited hardware support and preserves…
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2006
2006
A low-cost memory remapping scheme for address bus protection
Jun Yang
,
Lan Gao
,
Youtao Zhang
,
M. Chrobak
,
H. Lee
International Conference on Parallel…
2006
Corpus ID: 304434
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can…
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Highly Cited
2001
Highly Cited
2001
Pilchard — a reconfigurable computing platform with memory slot interface
P. H. W. Leong
,
M. P. Leong
,
+6 authors
mywong khleeg
IEEE Symposium on Field-Programmable Custom…
2001
Corpus ID: 17637085
A reconfigurable computing development environment called Pilchard, employing a field programmable gate array (FPGA) which plugs…
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1999
1999
Two High-Bandwidth Memory Bus Structures
J. Millar
,
P. Gillingham
IEEE Design & Test of Computers
1999
Corpus ID: 43165775
The authors evaluate two next-generation memory bus architectures approximating SLDRAM and Direct Rambus. Quantifying sources of…
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1998
1998
Making Network Interfaces Less Peripheral
Shubhendu S. Mukherjee
,
M. Hill
Computer
1998
Corpus ID: 8379838
A barrier to delivering improvements in network bandwidth and latency to users is the network interface (NI), which connects a…
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