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The gem5 simulator
- N. Binkert, Bradford M. Beckmann, D. Wood
- Computer ScienceCARN
- 31 May 2011
TLDR
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
- Milo M. K. Martin, D. Sorin, D. Wood
- Computer ScienceCARN
- 1 November 2005
TLDR
LogTM: log-based transactional memory
- Kevin E. Moore, J. Bobba, Michelle J. Moravan, M. Hill, D. Wood
- Computer ScienceThe Twelfth International Symposium on High…
- 27 February 2006
TLDR
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
- Luke Yen, J. Bobba, D. Wood
- Computer ScienceIEEE 13th International Symposium on High…
- 10 February 2007
TLDR
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
- Gabriel H. Loh, M. Hill
- Computer Science44th Annual IEEE/ACM International Symposium on…
- 3 December 2011
Die-stacking technology enables multiple layers of DRAM to be integrated with multicore processors. A promising use of stacked DRAM is as a cache, since its capacity is insufficient to be all of main…
Amdahl's Law in the Multicore Era
- M. Hill
- Computer ScienceComputer
- 1 July 2008
Augmenting Amdahl's law with a corollary for multicore hardware makes it relevant to future generations of chips with multiple processor cores. Obtaining optimal multicore performance will require…
A Primer on Memory Consistency and Cache Coherence
TLDR
Evaluating Associativity in CPU Caches
TLDR
DBMSs on a Modern Processor: Where Does Time Go?
- A. Ailamaki, D. DeWitt, M. Hill, D. Wood
- Computer ScienceVLDB
- 7 September 1999
TLDR
Weaving Relations for Cache Performance
- A. Ailamaki, D. DeWitt, M. Hill, Marios Skounakis
- Computer ScienceVLDB
- 11 September 2001
TLDR
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