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Logic optimization
Logic optimization, a part of logic synthesis in electronics, is the process of finding an equivalent representation of the specified logic circuit…
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Related topics
Related topics
14 relations
Binary decision diagram
Boolean algebra
Circuit minimization for Boolean functions
Combinational logic
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Broader (2)
Digital electronics
Electronic engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Block permutations in Boolean Space to minimize TCAM for packet classification
Rihua Wei
,
Yang Xu
,
H. Jonathan Chao
Proceedings IEEE INFOCOM
2012
Corpus ID: 11203096
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated…
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Highly Cited
2010
Highly Cited
2010
Design of AES S-box using combinational logic optimization
Nabihah Ahmad
,
Rezaul Hasan
,
W. M. Jubadi
IEEE Symposium on Industrial Electronics and…
2010
Corpus ID: 14073387
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is…
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2002
2002
Congestion minimization during placement without estimation
Bo Hu
,
M. Marek-Sadowska
International Conference on Computer Aided Design
2002
Corpus ID: 5689668
This paper presents a new congestion minimization technique for standard cell global placement. The most distinct feature of this…
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Review
2002
Review
2002
Timing and design closure in physical design flows
O. Coudert
Proceedings International Symposium on Quality…
2002
Corpus ID: 16618365
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints…
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2002
2002
Bridging the domains of high-level and logic synthesis
R. Bergamaschi
IEEE Trans. Comput. Aided Des. Integr. Circuits…
2002
Corpus ID: 7589964
High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level…
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2001
2001
Logic optimization of unidirectional circuits with structural methods
L. Entrena
,
C. López-Ongil
,
E. Olías
,
E. S. Millán
,
J. A. Espejo
Proceedings Seventh International On-Line Testing…
2001
Corpus ID: 6660083
Self-checking design based on unordered codes requires that the target circuit is transformed into a unidirectional circuit…
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1994
1994
Time-efficient automatic test pattern generation systems
B. So
1994
Corpus ID: 60036199
Automatic Test Pattern Generation (ATPG) systems are tools for generating tests for digital circuits. Due to the complexity of…
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1991
1991
Combinational logic optimization techniques in sequential logic synthesis
S. Malik
1991
Corpus ID: 58813612
Designing an integrated circuit with over one hundred thousand components is a significantly complicated task; impossible to…
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1991
1991
Timing optimization of multiphase sequential logic
K. Bartlett
,
G. Borriello
,
S. Raju
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1991
Corpus ID: 5494355
The timing optimization of multiphase logic entails the reduction of the overall cycle time of the machine and/or input-to-output…
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1988
1988
Experiments in logic optimization
M. Lightner
,
W. Wolf
[] IEEE International Conference on Computer…
1988
Corpus ID: 34313510
A number of experiments have been conducted to answer several important questions about logic optimization and its application to…
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