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Logic optimization

Logic optimization, a part of logic synthesis in electronics, is the process of finding an equivalent representation of the specified logic circuit… 
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Related topics

Related topics

14 relations
Binary decision diagramBoolean algebraCircuit minimization for Boolean functionsCombinational logic

Broader (2)

Digital electronicsElectronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2012
Highly Cited
2012
Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA
The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations… 
Highly Cited
2010
Highly Cited
2010
A New Combinational Logic Minimization Technique with Applications to Cryptology
A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the… 
Highly Cited
2010
Highly Cited
2010
Design of AES S-box using combinational logic optimization
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is… 
2008
2008
Resonant-Clock Latch-Based Design
This paper describes RF1 and RF2, two level-clocked test-chips that deploy resonant clocking to reduce power consumption in their… 
Review
2002
Review
2002
Logic, Optimization, and Constraint Programming
Because of their complementary strengths, optimization and constraint programming can be profitably merged. Their integration has… 
2002
2002
Congestion minimization during placement without estimation
This paper presents a new congestion minimization technique for standard cell global placement. The most distinct feature of this… 
Highly Cited
1994
Highly Cited
1994
Multi-level Logic Optimization By Implication Analysis
This paper proposes a new approach to multi-level logic optimization based on ATPG (Automatic Test Pattern Generation). Previous… 
Highly Cited
1993
Highly Cited
1993
Algorithms for Approximate FSM Traversal
In this paper we present algorithms for approximate FSM traversal based on state space decomposition. The original FSM is… 
Highly Cited
1993
Highly Cited
1993
Sequential logic optimization by redundancy addition and removal
This paper presents a method of multi-level logic optimization for combinational and synchronous sequential logic. The circuits… 
Highly Cited
1992
Highly Cited
1992
Synthesis of robust delay-fault-testable circuits: theory
The authors give a comprehensive theoretical framework for the analysis and synthesis of delay-fault-testable combinational logic… 
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