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Circuit minimization for Boolean functions
Known as:
Circuit minimization
, Logic circuit minimization
, Boolean minimization
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In Boolean algebra, circuit minimization is the problem of obtaining the smallest logic circuit (Boolean formula) that represents a given Boolean…
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Related topics
Related topics
17 relations
AND gate
Binary decision diagram
Circuit underutilization
Electronic circuit
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Broader (3)
Boolean algebra
Circuit complexity
Logic in computer science
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Angle and Waveform Estimation from Coarsely Quantized Array Data
Heng Zhu
,
Fangqing Liu
,
Jian Li
IEEE Vehicular Technology Conference
2019
Corpus ID: 207959816
We consider the problem of direction-of-arrival (DOA) and waveform estimation from coarsely quantized measurement samples…
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2013
2013
Design of locally-clocked asynchronous finite state machines using synchronous CAD tools
D. L. Oliveira
,
D. Bompean
,
T. Curtinhas
,
L. Faria
IEEE 4th Latin American Symposium on Circuits and…
2013
Corpus ID: 27378129
Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of embedded digital…
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2009
2009
Discontinuous penalty approach with deviation integral for global constrained minimization
Liu Chen
,
Yirong Yao
,
Q. Zheng
2009
Corpus ID: 109932011
In this paper, we use the discontinuous exact penalty functions to solve the constrained minimization problems with an integral…
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2002
2002
Paraconsistent Reasoning via Quantified Boolean Formulas , II : Circumscribing Inconsistent Theories ?
P. Besnard
,
Torsten Schaub
,
H. Tompits
,
S. Woltran
2002
Corpus ID: 16458468
Through minimal-model semantics, three-valued logics provide an interesting formalism for capturing reasoning from inconsistent…
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2000
2000
A scalable, loadable custom programmable logic device for solving Boolean satisfiability problems
M. J. Boyd
,
T. Larrabee
Proceedings IEEE Symposium on Field-Programmable…
2000
Corpus ID: 5841742
This paper introduces ELVIS, a custom PLD that solves Boolean satisfiability (SAT) problems and presents a significant…
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1998
1998
Multiple-valued logic minimization using universal literals and cost tables
Blair Fraser
,
G. Dueck
Proceedings. 28th IEEE International Symposium…
1998
Corpus ID: 15917888
We propose a minimization algorithm that combines cost tables and simulated annealing. Unlike other minimization procedures that…
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1992
1992
Minimal area merger of finite state machine controllers
Debaditya Mukherjee
,
Massoud Pedram
,
M. Breuer
European Design Automation Conference
1992
Corpus ID: 14893691
The authors present techniques for merging a pair of finite state machines (FSMs) that control the data-path circuitry on a chip…
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1991
1991
LSAT-an algorithm for the synthesis of two level threshold gate networks
Arlindo L. Oliveira
,
A. Sangiovanni-Vincentelli
IEEE International Conference on Computer-Aided…
1991
Corpus ID: 2237157
The authors present an algorithm for the synthesis of two-level threshold gate networks inspired by techniques used in classical…
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1990
1990
On the relationship between input encoding and logic minimization
Saeyang Yang
,
Maciej J. Ciesielski
Twenty-Third Annual Hawaii International…
1990
Corpus ID: 61029967
A theoretical formulation of the input encoding problem is presented, based on the concept of compatibility of dichotomies. Three…
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1990
1990
Automatic generation of don't cares for the controlling finite state machine from the corresponding behavioral description
M. Perkowski
,
J. E. Brown
IEEE International Symposium on Circuits and…
1990
Corpus ID: 61369664
A symbolic analysis method is described and applied to register-transfer microprograms describing control units of hardware…
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