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Latch-up
Known as:
Latchup
A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low…
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Related topics
Related topics
9 relations
Immunity-aware programming
Integrated circuit
Parasitic structure
Power cycling
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Study of system ESD codesign of a realistic mobile board
D. Johnsson
,
H. Gossner
EOS/ESD Symposium Proceedings
2011
Corpus ID: 6270543
Based on a mobile reference board a full system ESD IC/board codesign flow was examined. Accurate high current transient models…
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2006
2006
Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology
D. Kontos
,
K. Domanski
,
+6 authors
D. Alvarez
IEEE International Reliability Physics Symposium…
2006
Corpus ID: 1420666
In this work, the effect of design parameters on the internal and external latchup robustness of dual well (DW) and triple well…
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Highly Cited
2005
Highly Cited
2005
Effects of particle energy on proton-induced single-event latchup
J. Schwank
,
M. Shaneyfelt
,
+8 authors
E. Blackmore
IEEE Transactions on Nuclear Science
2005
Corpus ID: 20834705
The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton…
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Highly Cited
2003
Highly Cited
2003
CrossNets: possible neuromorphic networks based on nanoscale components
Özgür Türel
,
K. Likharev
International journal of circuit theory and…
2003
Corpus ID: 3983530
Extremely dense neuromorphic networks may be based on hybrid 2D arrays of nanoscale components, including molecular latching…
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Highly Cited
2002
Highly Cited
2002
Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies
P. Dodd
,
M. Shaneyfelt
,
J. Schwank
,
G. L. Hash
Digest. International Electron Devices Meeting,
2002
Corpus ID: 32794315
In this work we compare neutron-induced soft error rates (SER) and latchup in SRAMs from a variety of manufacturers. SER is found…
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1987
1987
High-speed BiCMOS technology with a buried twin well structure
T. Ikeda
,
A. Watanabe
,
+4 authors
K. Ogiue
IEEE Transactions on Electron Devices
1987
Corpus ID: 1923688
A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high…
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1986
1986
Numerical Simulation of SEU Induced Latch-Up
J. Rollins
,
W. Kolasinski
,
D. Marvin
,
R. Koga
IEEE Transactions on Nuclear Science
1986
Corpus ID: 34293493
The PISCES-II device analysis program has been modified to perform two-dimensional SEU induced latch-up simulations. The results…
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1985
1985
Latchup in CMOS Integrated Circuits
K. Soliman
,
D. Nichols
1985
Corpus ID: 60080414
Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary…
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Highly Cited
1983
Highly Cited
1983
A transient analysis of latchup in bulk CMOS
R. Troutman
,
H. Zappe
IEEE Transactions on Electron Devices
1983
Corpus ID: 13225927
This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage…
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Review
1974
Review
1974
Radiation effects on semiconductor devices
B. L. Gregory
,
C. Gwyn
1974
Corpus ID: 62555589
The radiation-induced degradation of semiconductor material parameters is reviewed. These results are related to the degradation…
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