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Latch-up

Known as: Latchup 
A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low… 
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Related topics

Related topics

9 relations
Immunity-aware programmingIntegrated circuitParasitic structurePower cycling

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2006
2006
Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS… 
2004
2004
The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology
  • S. VoldmanA. Watson
  • IEEE International Reliability Physics Symposium…
  • 2004
  • Corpus ID: 35212042
This paper will demonstrate the effect of deep trench (DT) on the latchup robustness of an 0.13 /spl mu/m 200 GHz BiCMOS SiGeC… 
Highly Cited
2003
Highly Cited
2003
CrossNets: possible neuromorphic networks based on nanoscale components
Extremely dense neuromorphic networks may be based on hybrid 2D arrays of nanoscale components, including molecular latching… 
Highly Cited
2002
Highly Cited
2002
Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies
In this work we compare neutron-induced soft error rates (SER) and latchup in SRAMs from a variety of manufacturers. SER is found… 
1994
1994
An automatic biasing scheme for tracing arbitrarily shaped I-V curves
A scheme for automated tracing of arbitrarily shaped I-V curves is presented. Tracing out the I-V curves for complicated device… 
1988
1988
Computation of steady-state CMOS latchup characteristics
Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation… 
1987
1987
High-speed BiCMOS technology with a buried twin well structure
A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high… 
1985
1985
Accurate trigger condition analysis for CMOS latchup
Two-dimensional device simulation is used to accurately predict both static and dynamic triggering conditions for CMOS latchup… 
1985
1985
Mechanisms for the Latchup Window Effect in Integrated Circuits
The latchup window effect has been studied in CMOS and advanced bipolar integrated circuits, using a 1.06 pm laser as a… 
Highly Cited
1984
Highly Cited
1984
Suppressing latchup in insulated gate transistors
Two-dimensional computer modeling of insulated gate transistor (IGT) structures has been used to demonstrate the suppression of… 
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