Skip to search formSkip to main contentSkip to account menu

Floorplan (microelectronics)

Known as: Floor planning, Floorplan (integrated circuits), Floorplanning 
In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional… 
Wikipedia (opens in a new tab)

Related topics

Related topics

17 relations
Arithmetic logic unitBarrel shifterBinary treeCPU cache

Broader (1)

Combinatorial optimization

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
In 3D ICs, TSV cross coupling can seriously degrade circuit performance if it is not sufficiently considered in a design. Cross… 
2012
2012
Statistical thermal modeling and optimization considering leakage power variations
Unaddressed thermal issues can seriously hinder the development of reliable and low power systems. In this paper, we propose a… 
2011
2011
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs
Voltage island has become a very effective design style for power saving in low-power design. However, the new design style also… 
2008
2008
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated… 
2007
2007
Microarchitecture Configurations and Floorplanning Co-Optimization
Microarchitecture configurations and floorplanning are keys to boost throughput, and they are strongly related. In this paper, we… 
2006
2006
A Revisit to Floorplan Optimization by Lagrangian Relaxation
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this… 
2004
2004
Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems
Three-dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a… 
Highly Cited
2000
Highly Cited
2000
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair
In this paper, we propose an adaptive genetic algorithm (GA) to solve the floorplanning problem in VLSI layout design, in which… 
1995
1995
Timing In(cid:13)uenced Force Directed Floorplanning
We present a timing driven (cid:13)oorplanning program for general cell layouts. The approach used combines quality of force… 
1988
1988
Generation of high speed CMOS multiplier-accumulators
The authors describe MAGGEN (multiplier-accumulator generator), a technology-independent generator for high-speed CMOS Wallace…