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Floorplan (microelectronics)

Known as: Floor planning, Floorplan (integrated circuits), Floorplanning 
In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional… 
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Related topics

Related topics

17 relations
Arithmetic logic unitBarrel shifterBinary treeCPU cache

Broader (1)

Combinatorial optimization

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A Multi-Granularity Power Modeling Methodology for Embedded Processors
With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to… 
Highly Cited
2007
Highly Cited
2007
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Power optimization is a crucial concern for modem circuit designs. Multiple supply voltages (MSV's) provide an effective… 
Highly Cited
2004
Highly Cited
2004
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and… 
Highly Cited
2003
Highly Cited
2003
Microarchitecture evaluation with physical planning
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the… 
Highly Cited
2003
Highly Cited
2003
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk… 
1999
1999
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
This paper presents DYNASTY–a new CAD framework aimed at supporting research of design techniques, algorithms and methodologies… 
1999
1999
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the… 
1998
1998
Evolutionary algorithms, simulated annealing, and Tabu search: a comparative study
Evolutionary algorithms, simulated annealing (SA), and Tabu Search (TS) are general iterative algorithms for combinatorial… 
Highly Cited
1992
Highly Cited
1992
Anatomy of a Silicon Compiler
1. Introduction and History R.W. Brodersen. Part I: Framework and Design Entry. 2. The OCT Data Manager R. Spickelmier, B.C… 
1990
1990
A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array
A 64-tap FIR (finite-impulse-response) digital filter fabricated in a 0.8- mu m, triple-level interconnect, BiCMOS gate-array… 
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