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Floorplan (microelectronics)
Known as:
Floor planning
, Floorplan (integrated circuits)
, Floorplanning
In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional…
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Related topics
Related topics
17 relations
Arithmetic logic unit
Barrel shifter
Binary tree
CPU cache
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Broader (1)
Combinatorial optimization
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Caleb Serafy
,
Ankur Srivastava
ACM International Symposium on Physical Design
2014
Corpus ID: 14395495
In 3D ICs, TSV cross coupling can seriously degrade circuit performance if it is not sufficiently considered in a design. Cross…
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2011
2011
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs
Qiang Zhou
,
Jin Shi
,
Bin Liu
,
Yici Cai
IEEE Transactions on Very Large Scale Integration…
2011
Corpus ID: 9532442
Voltage island has become a very effective design style for power saving in low-power design. However, the new design style also…
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2009
2009
Multicore parallel min-cost flow algorithm for CAD applications
Yinghai Lu
,
H. Zhou
,
L. Shang
,
Xuan Zeng
46th ACM/IEEE Design Automation Conference
2009
Corpus ID: 149251
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and many-core…
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2008
2008
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
M. Yoshikawa
,
Hironori Yamauchi
,
H. Terai
Engineering Letters
2008
Corpus ID: 6675105
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated…
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2006
2006
A Revisit to Floorplan Optimization by Lagrangian Relaxation
Chuan Lin
,
H. Zhou
,
C. Chu
IEEE/ACM International Conference on Computer…
2006
Corpus ID: 8618887
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this…
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2004
2004
Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems
M. Mukherjee
,
R. Vemuri
IEEE International Conference on Computer Design…
2004
Corpus ID: 10011914
Three-dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a…
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Highly Cited
2000
Highly Cited
2000
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair
S. Nakaya
,
T. Koide
,
S. Wakabayashi
IEEE International Symposium on Circuits and…
2000
Corpus ID: 22551574
In this paper, we propose an adaptive genetic algorithm (GA) to solve the floorplanning problem in VLSI layout design, in which…
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1997
1997
Regular datapaths on field programmable gate arrays
A. Koch
1997
Corpus ID: 45354245
Field-Programmable Gate Arrays (FPGAs) are a recent kind of programmable logic device. They allow the implementation of…
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1996
1996
Hybrid floorplanning based on partial clustering and module restructuring
T. Yamanouchi
,
Kazuo Tamakashi
,
T. Kambe
Proceedings of International Conference on…
1996
Corpus ID: 10723034
In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during…
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1995
1995
Timing In(cid:13)uenced Force Directed Floorplanning
H. Youssef
,
S. M. Sait
,
Khalid J. Al-Farra
1995
Corpus ID: 17637167
We present a timing driven (cid:13)oorplanning program for general cell layouts. The approach used combines quality of force…
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