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Floorplan (microelectronics)

Known as: Floor planning, Floorplan (integrated circuits), Floorplanning 
In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional… 
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Related topics

Related topics

17 relations
Arithmetic logic unitBarrel shifterBinary treeCPU cache

Broader (1)

Combinatorial optimization

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A Multi-Granularity Power Modeling Methodology for Embedded Processors
With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to… 
2008
2008
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated… 
2004
2004
Robust fixed-outline floorplanning through evolutionary search
In this paper, we address the pratical problem of fixed-outline VLSI floorplanning with minimizing the objective of area. This… 
Highly Cited
2003
Highly Cited
2003
Microarchitecture evaluation with physical planning
Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the… 
1999
1999
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the… 
1999
1999
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
This paper presents DYNASTY–a new CAD framework aimed at supporting research of design techniques, algorithms and methodologies… 
1998
1998
Evolutionary algorithms, simulated annealing, and Tabu search: a comparative study
Evolutionary algorithms, simulated annealing (SA), and Tabu Search (TS) are general iterative algorithms for combinatorial… 
1996
1996
Hybrid floorplanning based on partial clustering and module restructuring
In this paper, we propose a hybrid floorplanning methodology. Two hierarchical strategies for avoiding local optima during… 
Highly Cited
1992
Highly Cited
1992
Anatomy of a Silicon Compiler
1. Introduction and History R.W. Brodersen. Part I: Framework and Design Entry. 2. The OCT Data Manager R. Spickelmier, B.C… 
1990
1990
A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array
A 64-tap FIR (finite-impulse-response) digital filter fabricated in a 0.8- mu m, triple-level interconnect, BiCMOS gate-array… 
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