Digital delay line

Known as: Delay line, Digital delay 
A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed by a number of samples. If the delay is an… (More)
Wikipedia

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of… (More)
  • figure 2
  • figure 1
  • figure 5
  • figure 3
  • figure 4
Is this relevant?
2010
2010
This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
2009
Highly Cited
2009
We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
2007
Highly Cited
2007
A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
2006
Highly Cited
2006
This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked… (More)
  • figure 1
  • figure 3
  • figure 4
  • figure 5
  • figure 6
Is this relevant?
2005
2005
This paper presents a low power impulse generator design for ultra-wideband (UWB) impulse radio (IR) applications. Simple digital… (More)
  • figure 1
  • figure 3
  • figure 2
  • figure 4
  • figure 5
Is this relevant?
2002
2002
During the last few years, new synchronization techniques to send data between IC’s at increasingly high datarates have been… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
1995
1995
Two digital techniques have been developed to generate an internal clock signal from an external reference clock supplied to a… (More)
  • figure 1
  • figure 7
  • figure 9
  • figure 11
  • figure 14
Is this relevant?
Highly Cited
1988