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Digital delay line

Known as: Delay line, Digital delay 
A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed by a number of samples. If the delay is an… 
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Related topics

Related topics

6 relations
Analog delay lineCircular bufferDigital filterFinite impulse response

Broader (1)

Digital signal processing

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
High-Voltage Tolerant Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process
This paper reports a high-frequency DC-DC boost converter capable of sustaining up to 4× the rated process voltage using high… 
2011
2011
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC… 
2008
2008
A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs
This paper describes the design of a pulse-based ultra-wideband (UWB) transmitter for wireless personal area networks (WPANs… 
2003
2003
Statistical analysis of integrated passive delay lines
The statistical properties of integrated passive LC delay lines are investigated. A new variation using spiral inductors and… 
2003
2003
Digital Control for Power Factor Correction
This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC… 
Highly Cited
2002
Highly Cited
2002
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
We developed a 1-Gb/s/pin 512-Mb DDRII SDRAM composed of a digital delay-locked loop (DLL) and a slew-rate controlled output… 
Highly Cited
2001
Highly Cited
2001
Mitigating Short-Delay Multipath: a Promising New Technique
In the recent years, several advanced signal processing techniques have been devised to mitigate errors induced by multipath… 
1996
1996
Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology)
1993
1993
Synchronous CDMA for satellite frequency-selective broadcasting channels: Performance and receiver structures
The performance of a synchronous code division multiple access (S-CDMA) system in the presence of frequency-selective propagation… 
1993
1993
High-temperature superconducting delay lines and filters on sapphire and thinned LaAlO/sub 3/ substrates
The very low microwave surface resistance of high-temperature-superconductor (HTS) thin films allows the realization of microwave… 
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