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Digital delay line
Known as:
Delay line
, Digital delay
A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed by a number of samples. If the delay is an…
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Related topics
Related topics
6 relations
Analog delay line
Circular buffer
Digital filter
Finite impulse response
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Broader (1)
Digital signal processing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
Won-Joo Yun
,
Hyun-Woo Lee
,
Dongsuk Shin
,
Suki Kim
IEEE Transactions on Very Large Scale Integration…
2011
Corpus ID: 227449
This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC…
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2008
2008
A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs
M. Demirkan
,
R. Spencer
IEEE Journal of Solid-State Circuits
2008
Corpus ID: 36946998
This paper describes the design of a pulse-based ultra-wideband (UWB) transmitter for wireless personal area networks (WPANs…
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2003
2003
Statistical analysis of integrated passive delay lines
B. Analui
,
A. Hajimiri
Proceedings of the IEEE Custom Integrated…
2003
Corpus ID: 15324848
The statistical properties of integrated passive LC delay lines are investigated. A new variation using spiral inductors and…
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2003
2003
A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM
Jong-Tae Kwak
,
Chang-Ki Kwon
,
Kwan-Weon Kim
,
Seong-Hoon Lee
,
J. Kih
Symposium on VLSI Circuits. Digest of Technical…
2003
Corpus ID: 37580132
A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure…
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Highly Cited
2002
Highly Cited
2002
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
T. Matano
,
Y. Takai
,
+12 authors
K. Koyama
Symposium on VLSI Circuits. Digest of Technical…
2002
Corpus ID: 41790977
We developed a 1-Gb/s/pin 512-Mb DDRII SDRAM composed of a digital delay-locked loop (DLL) and a slew-rate controlled output…
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Highly Cited
2001
Highly Cited
2001
Mitigating Short-Delay Multipath: a Promising New Technique
J. Sleewaegen
,
F. Boon
2001
Corpus ID: 59030784
In the recent years, several advanced signal processing techniques have been devised to mitigate errors induced by multipath…
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1996
1996
Equaliser Performance for HIPERLAN in indoor channels
C. Tellambura
,
Y. Guo
,
S. Barton
Wireless personal communications
1996
Corpus ID: 46552951
In order to accomplish practical deployment modelling for system performance evaluation and comparison for possible modulation…
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1993
1993
Synchronous CDMA for satellite frequency-selective broadcasting channels: Performance and receiver structures
E. Colzi
,
C. Elia
,
F. Tarkoy
,
R. Viola
IEEE International Conference on Communications
1993
Corpus ID: 61572929
The performance of a synchronous code division multiple access (S-CDMA) system in the presence of frequency-selective propagation…
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1993
1993
High-temperature superconducting delay lines and filters on sapphire and thinned LaAlO/sub 3/ substrates
G. Liang
,
R. Withers
,
+4 authors
W. G. Lyons
IEEE transactions on applied superconductivity
1993
Corpus ID: 40559677
The very low microwave surface resistance of high-temperature-superconductor (HTS) thin films allows the realization of microwave…
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1966
1966
ULTRA WIDEBAND DIGITAL DELAY LINE
J. Payne
1966
Corpus ID: 66917845
Abstract : The report presents the detailed technical analysis, experimental results, and problems encountered in the design and…
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