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Digital delay line
Known as:
Delay line
, Digital delay
A digital delay line is a discrete element in digital filter theory, which allows a signal to be delayed by a number of samples. If the delay is an…
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Related topics
Related topics
6 relations
Analog delay line
Circular buffer
Digital filter
Finite impulse response
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Broader (1)
Digital signal processing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs
M. Demirkan
,
R. Spencer
IEEE Journal of Solid-State Circuits
2008
Corpus ID: 36946998
This paper describes the design of a pulse-based ultra-wideband (UWB) transmitter for wireless personal area networks (WPANs…
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2007
2007
Design of a Current Regulator with Extended Bandwidth for Servo Motor Drive
Anno Yoo
,
Y. Yoon
,
S. Sul
,
Masaki Hisatune
,
S. Morimoto
,
Kozo Ide
Power Conversion Conference - Nagoya
2007
Corpus ID: 25340926
To increase the productivity of the manufacturing process, the high bandwidth of the current regulation should be achieved. The…
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2003
2003
Digital Control for Power Factor Correction
Manjing Xie
2003
Corpus ID: 64741003
This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC…
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Highly Cited
2002
Highly Cited
2002
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
T. Matano
,
Y. Takai
,
+12 authors
K. Koyama
Symposium on VLSI Circuits. Digest of Technical…
2002
Corpus ID: 41790977
We developed a 1-Gb/s/pin 512-Mb DDRII SDRAM composed of a digital delay-locked loop (DLL) and a slew-rate controlled output…
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Highly Cited
2001
Highly Cited
2001
Mitigating Short-Delay Multipath: a Promising New Technique
J. Sleewaegen
,
F. Boon
2001
Corpus ID: 59030784
In the recent years, several advanced signal processing techniques have been devised to mitigate errors induced by multipath…
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1996
1996
Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface (Special Issue on ULSI Memory Technology)
Y. Okajima
,
M. Taguchi
,
M. Yanagawa
,
K. Nishimura
,
O. Hamada
1996
Corpus ID: 60157622
1993
1993
Synchronous CDMA for satellite frequency-selective broadcasting channels: Performance and receiver structures
E. Colzi
,
C. Elia
,
F. Tarkoy
,
R. Viola
IEEE International Conference on Communications
1993
Corpus ID: 61572929
The performance of a synchronous code division multiple access (S-CDMA) system in the presence of frequency-selective propagation…
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1993
1993
High-temperature superconducting delay lines and filters on sapphire and thinned LaAlO/sub 3/ substrates
G. Liang
,
R. Withers
,
+4 authors
W. G. Lyons
IEEE transactions on applied superconductivity
1993
Corpus ID: 40559677
The very low microwave surface resistance of high-temperature-superconductor (HTS) thin films allows the realization of microwave…
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1992
1992
Adaptive array antenna combined with tapped delay line using processing gain for spread-spectrum CDMA systems
R. Kohno
,
Hefeng Wang
,
H. Imai
[ Proceedings] The Third IEEE International…
1992
Corpus ID: 61658918
The paper first proposes a method to correctly update the weights of an adaptive array antenna using the inherent processing gain…
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1966
1966
ULTRA WIDEBAND DIGITAL DELAY LINE
J. Payne
1966
Corpus ID: 66917845
Abstract : The report presents the detailed technical analysis, experimental results, and problems encountered in the design and…
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