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Analog delay line
Known as:
Delay line
An analog delay line is a network of electrical components connected in series, where each individual element creates a time difference or phase…
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Related topics
Related topics
23 relations
Bendix G-15
Bucket-brigade device
Charge-coupled device
Delay line memory
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2007
2007
Reflective Amplified Recirculating Delay Line Bandpass Filter
E. Chan
,
R. Minasian
Journal of Lightwave Technology
2007
Corpus ID: 10743635
A new microwave photonic filter structure that can achieve a high factor, high stopband rejection, and high skirt selectivity…
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2006
2006
Design and System Demonstration of a Tunable Slow-Light Delay Line Based on Fiber Parametric Process
L. Yi
,
Weisheng Hu
,
Yikai Su
,
M. Gao
,
L. Leng
IEEE Photonics Technology Letters
2006
Corpus ID: 34501339
We design a tunable slow-light delay line based on fiber-optic parametric process by shaping the gain bandwidth, with its…
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2006
2006
Multistage Constructions of Linear Compressors, Non-Overtaking Delay Lines, and Flexible Delay Lines
Cheng-Shang Chang
,
Yi-Ting Chen
,
Jay Cheng
,
D. Lee
Proceedings IEEE INFOCOM . 25TH IEEE…
2006
Corpus ID: 6713319
Queueing theory is generally known as the theory to study the performance of queues. In this paper, we are interested in another…
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2004
2004
Hybrid analog-digital variable fiber-optic delay line
N. Riza
,
M. Arain
,
S.A. Khan
Journal of Lightwave Technology
2004
Corpus ID: 10467944
A variable fiber-optic delay line (VFODL) is introduced that, to the best of the authors' knowledge, is the first time that a…
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2004
2004
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
Y. Jeon
,
J. Lee
,
+4 authors
Hong-June Park
IEEE Journal of Solid-State Circuits
2004
Corpus ID: 45190075
The conventional register-controlled delay locked loop (RCDLL) with a single delay line requires a complex logic circuit…
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2004
2004
A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme
F. Baronti
,
D. Lunardini
,
R. Roncella
,
R. Saletti
IEEE Journal of Solid-State Circuits
2004
Corpus ID: 2501395
This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip…
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2002
2002
Contention resolution using multi-stage fiber delay line buffer in a photonic packet switch
H. Harai
,
N. Wada
,
F. Kubota
,
W. Chujo
IEEE International Conference on Communications…
2002
Corpus ID: 32712939
We focus on contention resolution using an optical fiber delay line (FDL) buffer in a photonic packet switch. A scheduler for…
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Highly Cited
2001
Highly Cited
2001
A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line
A. Chan
,
G. Roberts
Proceedings International Test Conference (Cat…
2001
Corpus ID: 206679689
In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay…
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Highly Cited
1997
Highly Cited
1997
A 1024-channel fast tunable delay line for ultrafast all-optical TDM networks
Kung-Li Deng
,
Koo Il Kang
,
I. Glask
,
P. Prucnal
IEEE Photonics Technology Letters
1997
Corpus ID: 33779347
Based on a passive k-stage feed-forward delay line structure, this letter presents a novel scheme which allows fast tuning among…
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1969
1969
Integrated MOS analog delay line
R. Mao
,
K. R. Keller
,
R. Ahrons
1969
Corpus ID: 61288723
A 16-stage, fixed or variable analog delay line that makes use of integrated p-channel MOS field-effect transistors is described…
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