Analog delay line

An analog delay line is a network of electrical components connected in series, where each individual element creates a time difference or phase… (More)
Wikipedia

Topic mentions per year

Topic mentions per year

1956-2017
05010015019562016

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Our research project is to design a readout IC for an ultrasonic transducer consisting of a matrix of more than 2000 elements… (More)
  • figure 1
  • figure 3
  • figure 2
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
2010
Highly Cited
2010
  • Jinyuan Wu
  • IEEE Transactions on Nuclear Science
  • 2010
This paper discusses implementation of the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
2010
2010
In this letter, we report the first on-chip design of an active dispersive delay line (DDL) based upon the distributed… (More)
  • figure 1
  • figure 3
  • table I
  • figure 4
  • figure 6
Is this relevant?
2009
2009
A compressive receiver (CR) is presented utilizing a composite right/left-handed (CRLH) dispersive delay line (DDL) for analog… (More)
  • figure 1
  • table I
  • figure 2
  • figure 3
  • figure 4
Is this relevant?
2009
2009
A reflection-type artificial dielectric substrate (ADS) microstrip dispersive delay line (DDL) for analog signal processing is… (More)
  • figure 2
  • figure 1
  • figure 3
  • figure 5
  • figure 4
Is this relevant?
2009
2009
In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
2006
2006
  • Meric Keskin
  • 2006 49th IEEE International Midwest Symposium on…
  • 2006
This paper presents a rail-to-rail, voltage-to-time conversion circuit, which can be used in time-analog-to-digital (TAD… (More)
  • figure 2
  • figure 3
  • figure 6
  • figure 4
  • figure 7
Is this relevant?
2004
2004
The design of an eight-channel 25 /spl mu/s wavelength-division-multiplexed (WDM) microwave photonic delay line is described. The… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • table I
Is this relevant?
Highly Cited
2000
Highly Cited
2000
This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 6
Is this relevant?
1994
1994
High performance analog building blocks are of great importance in mixed-mode ASIC's. The switched current approach allows their… (More)
  • figure 3
  • figure 5
  • table 1
Is this relevant?