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Circular buffer
Known as:
Ring
, Circular queue
, Ring (data structure)
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A circular buffer, circular queue, cyclic buffer or ring buffer is a data structure that uses a single, fixed-size buffer as if it were connected end…
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Related topics
Related topics
31 relations
Broader (1)
Computer memory
Data buffer
Data structure
Dictionary coder
Digital delay line
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
A Lightweight Network-based Android Malware Detection System
I. J. Sanz
,
Martin Andreoni Lopez
,
E. Viegas
,
Vinicius Rodrigues Sanches
IFIP Networking Conference (Networking)
2020
Corpus ID: 220668986
Over the last years, mobile devices became target of thousands of malicious applications. Since then, several works have proposed…
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2015
2015
Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs
Matthias Hiller
,
Ludwig Kurzinger
,
G. Sigl
,
Sven Müelich
,
S. Puchinger
,
M. Bossert
IEEE Computer Society Annual Symposium on VLSI
2015
Corpus ID: 18748703
Physical Unclonable Functions (PUFs) enable secure key storage for integrated circuits and FPGAs. PUF responses are noisy such…
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2014
2014
Bootstrap masker generation method for speech masking systems
Yosuke Kobayashi
,
K. Kondo
2014
Corpus ID: 4019190
Currently, speech masking systems make use of pre-recorded speech signals to generate maskers, which we call offline generated…
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2010
2010
EFFICIENT DIGITAL ENCRYPTION ALGORITHM BASED ON MATRIX SCRAMBLING TECHNIQUE
K. M
,
Mukthyar Azam S
,
S. Rasool
2010
Corpus ID: 16439438
This paper puts forward a safe mechanism of data transmission to tackle the security problem of information which is transmitted…
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2010
2010
Single-Producer/Single-Consumer Queues on Shared Cache Multi-Core Systems
M. Torquati
arXiv.org
2010
Corpus ID: 6717266
Using efficient point-to-point communication channels is critical for implementing fine grained parallel program on modern shared…
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2008
2008
A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS
M. Anders
,
S. Mathew
,
S. Hsu
,
R. Krishnamurthy
,
S. Borkar
IEEE Journal of Solid-State Circuits
2008
Corpus ID: 20354311
A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 Vt 90 nm dual-CMOS technology is described for 3…
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2006
2006
Novel low-overhead operand isolation techniques for low-power datapath synthesis
N. Banerjee
,
A. Raychowdhury
,
K. Roy
,
S. Bhunia
,
H. Mahmoodi
ICCD
2006
Corpus ID: 7843646
Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications…
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2005
2005
Dynamic Co-allocation Scheme for Parallel Data Transfer in Grid Environment
R. Bhuvaneswaran
,
Y. Katayama
,
N. Takahashi
First International Conference on Semantics…
2005
Corpus ID: 6644265
The large sized data sets are replicated in more than one site for the better availability to the nodes in a grid. Downloading…
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1977
1977
The interstage buffer storage capacity of non-powered assembly lines A simple mathematical approach
R. N. Basu
1977
Corpus ID: 62211188
This paper considers the properties of the interstage buffer storage capacity as a ‘ decoupling agent ’ in multi-station non…
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1971
1971
A Cyclic-Queue Model of System Overhead in Multiprogrammed Computer Systems
P. Lewis
,
G. Shedler
JACM
1971
Corpus ID: 13535925
A probabi l is t ic model is presented of a mul t ip rogrammed computer system operat ing under demand paging. The model contains…
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