Won-Joo Yun

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Digital DLLs are widely used for de-skewing external clocks and driver output clocks in memory applications. The DLL needs to have low jitter, low power consumption, and duty-cycle-correction (DCC) capability over a wide frequency range. The conventional digital DLL has a dual loop and a phase-blending mixer for DCC operation [1-5]. Even though the(More)
This paper describes some design techniques for high speed and low power pipelined 8-bit 250MSPS ADC. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. To reduce the power consumption and the die area, the number of(More)