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Dadda multiplier
Known as:
Dadda multipliers
, Dadda tree
The Dadda multiplier is a hardware multiplier design invented by computer scientist Luigi Dadda in 1965. It is similar to the Wallace multiplier, but…
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Related topics
Related topics
6 relations
Adder (electronics)
BKM algorithm
Binary multiplier
Booth's multiplication algorithm
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Dadda Multiplier designs using memristors
Lauren Guckert
,
E. Swartzlander
IEEE International Conference on IC Design and…
2017
Corpus ID: 42462903
Memristors have recently become a leader in future system design due to their unique storage abilities and high density. This…
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2015
2015
Low Power and Efficient Dadda Multiplier
S. Ravi
,
Govind Nair
,
R. Narayan
,
H. Kittur
2015
Corpus ID: 18015967
In this study an area optimized Dadda multiplier with a data aware Brent Kung adder in the final addition stage of the Dadda…
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Highly Cited
2012
Highly Cited
2012
Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
G. Kumar
,
V. Charishma
2012
Corpus ID: 7052712
This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have…
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2011
2011
Speed Comparison of 16x16 Vedic Multipliers
M. Pradhan
,
Rutuparna Panda
2011
Corpus ID: 9559332
The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then…
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Highly Cited
2010
Highly Cited
2010
Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs
Gang Zhou
,
H. Michalik
,
L. Hinsenkamp
IEEE Transactions on Very Large Scale Integration…
2010
Corpus ID: 19504561
This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate…
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2006
2006
A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor
Maurice Keller
,
R. Ronan
,
W. Marnane
,
Colin C. Murphy
IEEE International Conference on Reconfigurable…
2006
Corpus ID: 7938733
This paper details an architecture for performing inversion in the field GF(24m), which is the field used in computing the Tate…
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Highly Cited
2005
Highly Cited
2005
Novel design and reversible logic synthesis of multiplexer based full adder and multipliers
H. Thapliyal
,
M. Srinivas
48th Midwest Symposium on Circuits and Systems, .
2005
Corpus ID: 36417891
Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3/spl times/3…
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Highly Cited
2003
Highly Cited
2003
A comparison of Dadda and Wallace multiplier delays
W. J. Townsend
,
E. Swartzlander
,
J. Abraham
SPIE Optics + Photonics
2003
Corpus ID: 121437680
The two well-known fast multipliers are those presented by Wallace and Dadda. Both consist of three stages. In the first stage…
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Highly Cited
2003
Highly Cited
2003
Minimization of switching activities of partial products for designing low-power multipliers
O. Chen
,
Sandy Wang
,
Yi-Wen Wu
IEEE Trans. Very Large Scale Integr. Syst.
2003
Corpus ID: 44496102
This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the…
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Highly Cited
1983
Highly Cited
1983
A VLSI layout for a pipelined Dadda multiplier
P. Cappello
,
K. Steiglitz
TOCS
1983
Corpus ID: 8336684
Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design…
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