The Dadda multiplier is a hardware multiplier design invented by computer scientist Luigi Dadda in 1965. It is similar to the Wallace multiplier, butâ€¦Â (More)

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2017

2017

- Lauren Guckert, Earl E. Swartzlander
- 2017 IEEE International Conference on IC Designâ€¦
- 2017

Memristors have recently become a leader in future system design due to their unique storage abilities and high density. Thisâ€¦Â (More)

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2015

2015

In this study an area optimized Dadda multiplier with a data aware Brent Kung adder in the final addition stage of the Daddaâ€¦Â (More)

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2014

2014

- Girija Alukuru, J. Ravinder Raju, Anilkumar Somasi
- 2014

Floating-point unit (FPU) is one of the most important custom applications needed in most hardware designs as it adds accuracyâ€¦Â (More)

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2013

2013

- Beena Patricia Jeevan, S. Narender, Chandan K. Reddy, K. Sivani
- 2013 International Mutli-Conference on Automationâ€¦
- 2013

This paper presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication ofâ€¦Â (More)

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2013

2013

- P. Samundiswary
- 2013

Multiplier is an important circuit used in electronic industry especially in digital signal processing operations such asâ€¦Â (More)

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2013

2013

- Bharat Kumar Potipireddi, Abhijit R. Asati
- 2013

Dadda multipliers are among the fastest multipliers owing to their logarithmic delay. The partial products of twoâ€Ÿs complementâ€¦Â (More)

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2011

2011

AbstractIn this work faster column compression multiplication has been achieved by using a combination of two design techniquesâ€¦Â (More)

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2011

2011

- Addanki Purna Ramesh
- 2011

The heart of the MAC unit is the multiplier. Multipliers are the fundamental components in all digital processing systems. Manyâ€¦Â (More)

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2010

2010

- Seong-Wan Kim, Earl E. Swartzlander
- 10th IEEE International Conference onâ€¦
- 2010

This paper explores the design of parallel multipliers for Quantum-Dot Cellular Automata. Array multipliers, Wallace multipliersâ€¦Â (More)

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1983

1983

- Peter R. Cappello, Kenneth Steiglitz
- ACM Trans. Comput. Syst.
- 1983

Parallel counters (unary-to-binary converters) are the principal component of a Dadda multiplier. We specify a design first for aâ€¦Â (More)

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