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Dadda multiplier

Known as: Dadda multipliers, Dadda tree 
The Dadda multiplier is a hardware multiplier design invented by computer scientist Luigi Dadda in 1965. It is similar to the Wallace multiplier, but… Expand
Wikipedia

Related topics

Related topics

6 relations
Adder (electronics)BKM algorithmBinary multiplierBooth's multiplication algorithm
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
A high speed binary floating point multiplier using Dadda algorithm
This paper presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of… Expand
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Highly Cited
2012
Highly Cited
2012
Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have… Expand
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2011
2011
Speed Comparison of 16x16 Vedic Multipliers
The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then… Expand
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2010
2010
A High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree
Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication… Expand
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2010
2010
Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs
This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate… Expand
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Highly Cited
2005
Highly Cited
2005
Novel design and reversible logic synthesis of multiplexer based full adder and multipliers
Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3/spl times/3… Expand
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Highly Cited
2003
Highly Cited
2003
A comparison of Dadda and Wallace multiplier delays
The two well-known fast multipliers are those presented by Wallace and Dadda. Both consist of three stages. In the first stage… Expand
Highly Cited
2003
Highly Cited
2003
Minimization of switching activities of partial products for designing low-power multipliers
This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the… Expand
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1996
1996
A new VLSI architecture for perceptron network
A new architecture for multilayer perceptron network called the sliding feeder perceptron neural network is proposed. The sliding… Expand
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Highly Cited
1983
Highly Cited
1983
A VLSI layout for a pipelined Dadda multiplier
Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design… Expand
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