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This paper presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of… Expand This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have… Expand The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then… Expand Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication… Expand This paper presents complexity analysis [both in application-specific integrated circuits (ASICs) and on field-programmable gate… Expand Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3/spl times/3… Expand The two well-known fast multipliers are those presented by Wallace and Dadda. Both consist of three stages. In the first stage… Expand This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the… Expand A new architecture for multilayer perceptron network called the sliding feeder perceptron neural network is proposed. The sliding… Expand Parallel counters (unary-to-binary converters) are the principal component of a dadda multiplier. The authors specify a design… Expand