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Coprocessor
Known as:
Processor
, Co-processor
, Math co-processor
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A coprocessor is a computer processor used to supplement the functions of the primary processor (the CPU). Operations performed by the coprocessor…
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Related topics
Related topics
50 relations
ARM architecture
ARMulator
Apple A7
Apple A9
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Broader (1)
Central processing unit
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
Early Experience on Porting and Running a Lattice Boltzmann Code on the Xeon-Phi Co-Processor
G. Crimi
,
F. Mantovani
,
M. Pivanti
,
S. Schifano
,
R. Tripiccione
International Conference on Conceptual Structures
2013
Corpus ID: 29558228
Highly Cited
2011
Highly Cited
2011
FPGA Implementations of the AES Masked Against Power Analysis Attacks
F. Regazzoni
,
Yi (Estelle) Wang
,
François-Xavier Standaert
2011
Corpus ID: 5752393
Power analysis attacks are a serious treat for implementations of modern cryptographic algorithms. Masking is a particularly…
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Highly Cited
2010
Highly Cited
2010
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage
Y. Pu
,
J. P. D. Gyvez
,
H. Corporaal
,
Yajun Ha
IEEE Journal of Solid-State Circuits
2010
Corpus ID: 6179497
We present a design technique for (near) subthreshold operation that achieves ultra low energy dissipation at throughputs of up…
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Highly Cited
2009
Highly Cited
2009
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module
L. Sauvage
,
S. Guilley
,
Y. Mathieu
TRETS
2009
Corpus ID: 17187675
Since the first announcement of a Side Channel Analysis (SCA) about ten years ago, considerable research has been devoted to…
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Highly Cited
2007
Highly Cited
2007
955-fps Real-time Shape Measurement of a Moving/Deforming Object using High-speed Vision for Numerous-point Analysis
Yoshihiro Watanabe
,
T. Komuro
,
M. Ishikawa
Proceedings IEEE International Conference on…
2007
Corpus ID: 6921307
This paper describes real-time shape measurement using a newly developed high-speed vision system. Our proposed measurement…
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Highly Cited
2007
Highly Cited
2007
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
Christopher Claus
,
Florian Helmut Müller
,
J. Zeppenfeld
,
W. Stechele
IEEE International Parallel and Distributed…
2007
Corpus ID: 8617311
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial…
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Highly Cited
1999
Highly Cited
1999
A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP
B. Ackland
,
A. Anesko
,
+13 authors
Joseph Jay Williams
Proceedings of the IEEE Custom Integrated…
1999
Corpus ID: 70139877
A MIMD multiprocessor DSP chip containing four 64-b processing elements (PEs) interconnected by a 128-b pipelined split…
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Highly Cited
1996
Highly Cited
1996
The COSYMA environment for hardware/software cosynthesis of small embedded systems
R. Ernst
,
J. Henkel
,
+4 authors
M. Trawny
Microprocessors and microsystems
1996
Corpus ID: 31816678
Highly Cited
1995
Highly Cited
1995
Experience with active messages on the Meiko CS-2
K. Schauser
,
C. Scheiman
Proceedings of 9th International Parallel…
1995
Corpus ID: 5474053
Active messages provide a low latency communication architecture which on modern parallel machines achieves more than an order of…
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Review
1985
Review
1985
Performance studies of a Prolog machine architecture
T. Dobry
,
A. Despain
,
Y. Patt
International Symposium on Computer Architecture
1985
Corpus ID: 14367172
The PLM is a co-processor a r c h i t e c t u r e designed for efficient execu t ion of Prolog programs. It is the first p ro to…
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