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Constraint graph (layout)
Known as:
Horizontal constraint graph
, Vertical constraint graph
In some tasks of integrated circuit layout design a necessity arises to optimize placement of non-overlapping objects in the plane. In general this…
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Related topics
Related topics
6 relations
Directed graph
Floorplan (microelectronics)
Integrated circuit
Integrated circuit layout
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Papers overview
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2004
2004
Optimal Bubble Sort Based Non-Manhattan Channel Router
Sean M. Pieper
2004
Corpus ID: 61967080
Historically, channel routers have limited themselves to Manhattan routing. This has resulted in inefficiencies, particularly in…
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1998
1998
Local optimality theory in VLSI channel routing: composite cyclic vertical constraints
A. D. Johnson
Proceedings of the 8th Great Lakes Symposium on…
1998
Corpus ID: 11024922
Local Optimality paradigm is applicable to all combinatorial optimization problems. Its direct field of application are the…
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1997
1997
An efficient paired-net routing algorithm for high-speed bipolar LSIs
Y. Takei
,
A. Onozawa
,
K. Kawai
,
H. Kitazawa
Proceedings Great Lakes Symposium on VLSI
1997
Corpus ID: 10358416
This paper proposes an efficient paired-net routing algorithm. A paired net consists of two nets assigned to adjacent tracks and…
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1996
1996
On locally optimal breaking of complex cyclic vertical constraints in VLSI channel routing
A. D. Johnson
Proceedings of the Sixth Great Lakes Symposium on…
1996
Corpus ID: 38135642
Existing theory has supported deterministic polynomial time procedures for locally optimal breaking (LOB) of two classes of…
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1995
1995
On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing
A. D. Johnson
Proceedings. Fifth Great Lakes Symposium on VLSI
1995
Corpus ID: 3154017
Locally optimal breaking strategy was already developed for disjoint directed circuits in the vertical constraint graph. The…
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1993
1993
Modeling the vertical constraints in VLSI channel routing
Antonije D. Jovanovic
[] Proceedings Third Great Lakes Symposium on…
1993
Corpus ID: 27407442
Demonstrates that the vertical constraint graph (VCG) is not a complete representation of the vertical constraints of a channel…
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1991
1991
A hierarchical methodology to improve channel routing by pin permutation
C. Y. Hou
,
C. Y. Chen
IEEE International Conference on Computer-Aided…
1991
Corpus ID: 19100137
A hierarchical pin permutation algorithm is presented which is used as a preprocessor of conventional channel routing algorithms…
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1985
1985
A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays
M. Terai
IEEE Transactions on Computer-Aided Design of…
1985
Corpus ID: 15465353
The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively…
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