Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 237,159,865 papers from all fields of science
Search
Sign In
Create Free Account
Universal Verification Methodology
Known as:
UVM (disambiguation)
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
5 relations
ERM (e Reuse Methodology)
Electronic design automation
Integrated circuit
Open Verification Methodology
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Automated UVM Based Verification of Device Life Cycle Management IP
Srivasthav Kotha
,
Raji Ravimony
,
N. Mohankumar
Advances in Intelligent Systems and Computing
2019
Corpus ID: 208094242
Device lifecycle management intellectual property (IP) is used to configure the generic register transfer level (RTL) based on…
Expand
2019
2019
Case study on Universal Verification Methodology(UVM) SystemC testbench for RTL verification
Kevin Chacko
2019
Corpus ID: 204081864
This Master’s thesis aims to conduct a case study on using Universal Verification Methodology (UVM) in SystemC for Register…
Expand
2018
2018
A Reusable Functional Simulation Verification Method Based on UVM for FPGA Products in DAS
Xiuting Lv
,
Yun-tao Zhang
,
Zongsheng Cao
,
Fei Wu
,
Lingfeng Dong
Lecture Notes in Electrical Engineering
2018
Corpus ID: 131896946
Functional simulation verification is an important part for Field Programmable Gate Array (FPGA) product verification. Many…
Expand
2017
2017
Using Python Tools to Assist Mixed-Signal ASIC Design and Verification Methodologies
Evangelos Logaras
,
Andreas Weitzer
Austrochip Workshop on Microelectronics…
2017
Corpus ID: 23321954
We present a set of tools for digital design, integration and verification of mixed-signal Application Specific Integrated…
Expand
2017
2017
VERIFICATION OF RISC-V PROCESSOR USING UVM TESTBENCH
C. Anilkumar
,
K. Venkateswarlu
2017
Corpus ID: 212577310
RISC-V (pronounced "risk-five") is a new, open, and completely free general-purpose instruction set architecture (ISA) developed…
Expand
2016
2016
Development of a Massively Parallel Coarse Grained Reconfigurable Fabric verification Environment using Universal Verification Methodology
A. Jayabalan
2016
Corpus ID: 208107988
According to the International Roadmap for semiconductors (ITRS), there should be a 1000X improvement in performance with only…
Expand
2016
2016
Ethernet MAC Verification by Efficient Verification Methodology for SOC Performance Improvement
S. Chitti
,
P. Chandrasekhar
,
M. Asharani
,
G. Krishnamurthy
2016
Corpus ID: 61413537
Verification of Gigabit Ethernet Media Access Control (MAC), part of most of the networking SOC is accomplished by using the most…
Expand
Review
2014
Review
2014
REVIEW ON UNIVERSAL VERIFICATION METHODOLOGY (UVM) CONCEPTS FOR FUNCTIONAL VERIFICATION
Siddharth Raghuvanshi
,
Viswajeet Singh
2014
Corpus ID: 212457756
-The main goal of functional verification in hardware design is to find out the bugs in design description given by design…
Expand
2014
2014
UVM (Universal Verification methodology) based RFCTRL interface testing platform and testing method
茅乾博
2014
Corpus ID: 70271294
The present invention discloses a UVM (Universal Verification methodology) based RFCTRL interface testing platform. The platform…
Expand
2013
2013
Verification of USB 3 . 0 Device IP using Universal Verification Methodology
K. Kapadiya
2013
Corpus ID: 4285282
Verification of integrated USB 2.0 – USB 3.0 Device IP by developing device reference module connected to XDC side and ready to…
Expand