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Trace scheduling
Trace scheduling is an optimization technique used in compilers for computer programs. A compiler often can, by rearranging its generated machine…
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Related topics
Related topics
5 relations
Instruction scheduling
Loop unrolling
Multiflow
ST200 family
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction
R. Grishman
,
B. Su
IEEE transactions on computers
2018
Corpus ID: 2779494
Fisher has recently described a new procedure for global microcode compaction which he calls "trace scheduling." We have…
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2004
2004
The Performance Potential of Trace-based Dynamic Optimization
Brian Fahs
,
Aqeel Mahesri
,
Francesco Spadini
,
Sanjay J. Patel
,
S. Lumetta
2004
Corpus ID: 18260609
Dynamic optimization can apply powerful optimizations to h ot execution paths that span traditional boundaries such as branches…
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Review
2003
Review
2003
CSE 231 project report —-survey on instruction scheduling
Yang Yang
2003
Corpus ID: 14549643
This paper surveys past research on instruction scheduling for exploiting more Instruction Level Parallelism (ILP). We focus on…
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2002
2002
On the Benefits of Speculative Trace Scheduling in VLIW Processors
Manvi Agarwal
,
S. Nandy
,
J. V. Eijndhoven
,
S. Balakrishnan
International Conference on Parallel and…
2002
Corpus ID: 11091693
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We…
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2002
2002
Speculative trace scheduling in VLIW processors
Manvi Agarwal
,
S. Nandy
,
J. V. Eijndhoven
,
S. Balakrishnan
Proceedings. IEEE International Conference on…
2002
Corpus ID: 22948
VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the…
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2001
2001
EPIC Instruction Scheduling Based on Optimal Approaches
Steve Haga
,
R. Barua
2001
Corpus ID: 10623542
This paper presents a method for instruction scheduling that considers the scheduling restrictions inherent in VLIW processors…
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2000
2000
Optimizing the cache performance of non-numeric applications
C. Luk
2000
Corpus ID: 60660107
The latency of accessing instructions and data from the memory subsystem is an increasingly crucial performance bottleneck in…
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1999
1999
Performance Limits of Trace Caches
M. Postiff
,
G. Tyson
,
T. Mudge
J. Instr. Level Parallelism
1999
Corpus ID: 1799826
A growing number of studies have explored the use o f trace caches as a mechanism to increase instruction fetch bandwidth. The…
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1992
1992
Low level scheduling using the hierarchical task graph
D. Wallace
International Conference on Supercomputing
1992
Corpus ID: 14181371
This paper introduces a new efficient instruction scheduling algorithm that can schedule across basic blocks. Scheduling globally…
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1984
1984
Parallelism, memory anti-aliasing and correctness for trace scheduling compilers (disambiguation, flow-analysis, compaction)
A. Nicolau
1984
Corpus ID: 207927918
Trace scheduling 12 is a technique for transforming sequential programs into parallel code. When this investigation began, trace…
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