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Trace scheduling
Trace scheduling is an optimization technique used in compilers for computer programs. A compiler often can, by rearranging its generated machine…
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Related topics
Related topics
5 relations
Instruction scheduling
Loop unrolling
Multiflow
ST200 family
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Warp-aware trace scheduling for GPUs
James A. Jablin
,
T. Jablin
,
O. Mutlu
,
M. Herlihy
International Conference on Parallel…
2014
Corpus ID: 14658963
GPU performance depends not only on thread/warp level parallelism (TLP) but also on instruction-level parallelism (ILP). It is…
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2006
2006
Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging
A. C. S. Beck
,
Victor B. F. Gomes
,
L. Carro
IFIP International Conference on Very Large Scale…
2006
Corpus ID: 20164517
As Moore's law is loosing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power…
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2004
2004
Instruction Scheduling for Low Power
A. Parikh
,
Soontae Kim
,
M. Kandemir
,
N. Vijaykrishnan
,
M. Irwin
J. VLSI Signal Process.
2004
Corpus ID: 18186906
Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although…
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1999
1999
Performance Limits of Trace Caches
M. Postiff
,
G. Tyson
,
T. Mudge
J. Instr. Level Parallelism
1999
Corpus ID: 1799826
A growing number of studies have explored the use o f trace caches as a mechanism to increase instruction fetch bandwidth. The…
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Highly Cited
1993
Highly Cited
1993
The multiflow trace scheduling compiler
P. G. Lowney
,
S. Freudenberger
,
+4 authors
J. Ruttenberg
Journal of Supercomputing
1993
Corpus ID: 26787960
The Multiflow compiler uses the trace scheduling algorithm to find and exploit instruction-level parallelism beyond basic blocks…
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1993
1993
Hardware and software for functional and fine grain parallelism
C. Beckmann
1993
Corpus ID: 61133699
This thesis examines nonloop parallelism at both fine and coarse levels of granularity in numerical FORTRAN programs…
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Highly Cited
1988
Highly Cited
1988
Software pipelining: an effective scheduling technique for VLIW machines
M. Lam
ACM-SIGPLAN Symposium on Programming Language…
1988
Corpus ID: 14463205
This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software…
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Highly Cited
1987
Highly Cited
1987
A VLIW architecture for a trace scheduling compiler
R. Colwell
,
Robert P. Nix
,
J. O'Donnell
,
David B. Papworth
,
P. Rodman
IEEE Trans. Computers
1987
Corpus ID: 5503383
Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current…
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1984
1984
Parallelism, memory anti-aliasing and correctness for trace scheduling compilers (disambiguation, flow-analysis, compaction)
A. Nicolau
1984
Corpus ID: 207927918
Trace scheduling 12 is a technique for transforming sequential programs into parallel code. When this investigation began, trace…
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Highly Cited
1981
Highly Cited
1981
Trace Scheduling: A Technique for Global Microcode Compaction
J. A. Fisher
IEEE transactions on computers
1981
Corpus ID: 1650655
Microcode compaction is the conversion of sequential microcode into efficient parallel (horizontal) microcode. Local compaction…
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