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Timing closure

Known as: Physical timing closure, Timing simulation 
Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by… 
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Related topics

Related topics

10 relations
Computer-aided designDesign closureDesign flow (EDA)Electronic design automation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
A 256-Mcell Phase-Change Memory Chip Operating at $2{+}$ Bit/Cell
A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on… 
2011
2011
The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator
The high-level modeling and parameterization capabilities of current hardware description languages, as well as the huge… 
Highly Cited
2008
Highly Cited
2008
The Rubus component model for resource constrained real-time systems
In this paper we present a component model for development of distributed real-time systems. The model is developed to support… 
Review
2008
Review
2008
CMP Fill Synthesis: A Survey of Recent Studies
We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill synthesis, in terms of both… 
2007
2007
Computing Synchronizer Failure Probabilities
System-on-chip designs often have a large number of timing domains. Communication between these domains requires synchronization… 
2004
2004
Timing closure through a globally synchronous, timing partitioned design methodology
A method to mitigate timing problems due to global wire delays is proposed. The method follows closely a fully synchronous design… 
2003
2003
Word-level intelligibility of time-compressed speech: prosodic and segmental factors
Highly Cited
2000
Highly Cited
2000
Modelling evaporation and drift losses in irrigation with medium size impact sprinklers under semi-arid conditions
Highly Cited
1992
Highly Cited
1992
ALLIANCE: A complete Set of CAD Tools for teaching VLSI Design
a timing analyzer, an interactive generator debugger, full-custom generators, and a test coverage tool. Ongoing researches are… 
Highly Cited
1987
Highly Cited
1987
Parallel bit-level pipelined VLSI designs for high-speed signal processing
This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in… 
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