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Test vector
In computer science and engineering, a test vector is a set of inputs provided to a system in order to test that system.
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9 relations
All-pairs testing
Boundary-value analysis
Computable function
Computer science
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Computer engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects
Biswajit Bhowmik
,
S. Biswas
,
J. Deka
23rd Mediterranean Conference on Control and…
2015
Corpus ID: 16628809
With the rapid advancements of deep submicron and nano technologies the dimension of a chip is ever shrinking. With continuous…
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2008
2008
Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers
E. Erdogan
,
S. Ozev
IEEE VLSI Test Symposium
2008
Corpus ID: 25756758
This paper presents a loop-back method for quadrature modulation transceiver circuits to diagnose parametric faults of the system…
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2008
2008
Polymorphic Gates in Design and Test of Digital Circuits
L. Sekanina
,
Lukás Starecek
,
Z. Kotásek
,
Z. Gajda
International Journal of Unconventional Computing
2008
Corpus ID: 18797266
A rolling-bearing-mounted linear guiding unit comprising a hardened and polished guide rail on which rolling element raceways are…
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2007
2007
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits
G. Venayagamoorthy
,
S. Smith
,
G. Singhal
Engineering applications of artificial…
2007
Corpus ID: 2793465
Highly Cited
2005
Highly Cited
2005
X-filter: filtering unknowns from compacted test responses
Manish Sharma
,
Wu-Tung Cheng
IEEE International Conference on Test, .
2005
Corpus ID: 24233821
Using off-the-shelf error correcting codes for compacting test response (Patel, 2003) is attractive because it provides multiple…
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2005
2005
On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios
Huaxing Tang
,
Chen Wang
,
J. Rajski
,
S. Reddy
,
J. Tyszer
,
I. Pomeranz
18th International Conference on VLSI Design held…
2005
Corpus ID: 9351983
We propose an enhanced selective compaction scheme, which integrates three techniques, called selectively filled tests, selective…
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2002
2002
Scan power reduction through test data transition frequency analysis
O. Sinanoglu
,
I. Bayraktaroglu
,
A. Orailoglu
Proceedings. International Test Conference
2002
Corpus ID: 18183200
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of…
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2002
2002
Timed test generation for crosstalk switch failures in domino CMOS
R. Kundu
,
R. D. Blanton
Proceedings 20th IEEE VLSI Test Symposium (VTS )
2002
Corpus ID: 40454672
As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem…
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1999
1999
Automatic test case generation from requirements specifications for real-time embedded systems
Steven J. Cunning
,
J. Rozenblit
IEEE SMC'99 Conference Proceedings. IEEE…
1999
Corpus ID: 8367444
This paper presents continuing research toward automatic generation of test cases from requirements specifications for event…
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1997
1997
Using Partial Isolation Rings to Test Core-Based Designs
N. Touba
,
B. Pouya
IEEE Design & Test of Computers
1997
Corpus ID: 38063457
A partial isolation ring provides the same fault coverage as a full isolation ring but avoids adding multiplexers on critical…
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