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A mechanism for online diagnosis of hard faults in microprocessors
TLDR
A reliable microprocessor design is developed that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy by leveraging DIVA dynamic verification and a new scheme for diagnosing hard faults.
Tolerating hard faults in microprocessor array structures
In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch
Detailed Characterization of Transceiver Parameters Through Loop-Back-Based BiST
  • E. Erdogan, S. Ozev
  • Computer Science
    IEEE Transactions on Very Large Scale Integration…
  • 1 June 2010
TLDR
A built-in-self-test (BiST) solution for quadrature modulation transceiver circuits using only transmitter and receiver baseband signals for test analysis using the NLS method and detailed nonlinear system modeling is presented.
Experimental and Simulated Cycling of ISFET Electric Fields for Drift Reset
We demonstrate the cycling of electric fields within an ion-sensitive field-effect transistor (ISFET) as a method to control drift. ISFETs had a repeatable drift pattern when cycling the vertical
Testing of droplet-based microelectrofluidic systems
TLDR
This paper presents a costeffective concurrent test methodology for droplet-based microelectrofluidic systems, presents a classification of catastrophic and parametric faults in such systems and shows how faults can be detected by electrostatically controlling and tracking droplet motion.
Concurrent testing of digital microfluidics-based biochips
TLDR
The proposed concurrent testing methodology is directed at ensuring high reliability and availability of bio-MEMS and lab-on-a-chip systems, as they are increasingly deployed for safety-critical applications.
An ADC-BiST Scheme Using Sequential Code Analysis
  • E. Erdogan, S. Ozev
  • Computer Science
    Design, Automation & Test in Europe Conference…
  • 16 April 2007
TLDR
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis and presents two implementation options based on how much on-chip resources are available.
Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance
TLDR
A stealth circuit for unauthorized transmissions which can be hidden within the legitimate signal and does not alter the circuit performance while being easily detectable by the malicious receiver is presented.
Rail Clamp with Dynamic Time-Constant Adjustment
A dual time-constant rail clamp for protecting CMOS circuits during electrostatic discharge (ESD) events is described. In the new circuit, a relatively small time constant is dynamically adjusted
Ensuring the operational health of droplet-based microelectrofluidic biosensor systems
Recent events have heightened the need for fast, accurate, and reliable biological/chemical sensor systems for critical locations. As droplet-based microelectrofluidic sensor systems become
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