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Super Harvard Architecture Single-Chip Computer
Known as:
Super harvard
, SHARC (chip)
, Super harvard architecture
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The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is…
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24 relations
32-bit
48-bit
Assembly language
Blackfin
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2009
2009
Boot Kernel Customization and Firmware Upgradeability on SHARC® Processors
Mitesh Moonat
2009
Corpus ID: 62752201
Copyright 2000-2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product…
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2008
2008
Efficient On-Trip Timetable Information in the Presence of Delays
L. Frede
,
M. Müller-Hannemann
,
Mathias Schnee
Algorithmic Approaches for Transportation…
2008
Corpus ID: 17290481
The search for train connections in state-of-the-art commercial timetable information systems is based on a static schedule…
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2007
2007
SHARC-II 350 μm OBSERVATIONS OF THERMAL EMISSION FROM WARM DUST IN z ⩾ 5 QUASARS
Ran Wang
,
J. Wagg
,
+10 authors
Linhua Jiang
2007
Corpus ID: 118447402
We present observations of four z ⩾ 5 SDSS quasars at 350 μm with the SHARC-II bolometer camera on the Caltech Submillimeter…
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2005
2005
Design of a high-quality audio-specific DSP core
Suk Hyun Yoon
,
M. Sunwoo
,
J. Moon
IEEE Workshop on Signal Processing Systems Design…
2005
Corpus ID: 18717537
This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality…
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2004
2004
Rapid prototyping tools for power electronic systems: demonstration with shunt active power filters
J. Jacobs
,
D. Detjen
,
Claus-Ulrich Karipidis
,
R. D. De Doncker
IEEE transactions on power electronics
2004
Corpus ID: 9338541
This paper presents three new rapid prototyping tools to develop power electronic systems. The effectiveness of these tools is…
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2004
2004
Sensorless stand alone variable speed system for distributed generation
G. Iwański
,
W. Koczara
IEEE 35th Annual Power Electronics Specialists…
2004
Corpus ID: 24776536
The following paper presents a variable speed stand alone power generating system. The system consists of a double fed induction…
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2003
2003
TDL: A Hardware Description Language for Retargetable Postpass Optimizations and Analyses
Daniel Kästner
International Conference on Generative…
2003
Corpus ID: 724497
The hardware description language TDL has been designed with the goal to generate machine-dependent postpass optimizers and…
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2002
2002
Architecture Description Languages for Retargetable Compilation
W. Qin
,
S. Malik
The Compiler Design Handbook
2002
Corpus ID: 47095256
2001
2001
An empirical evaluation of high level transformations for embedded processors
Björn Franke
,
M. O’Boyle
International Conference on Compilers…
2001
Corpus ID: 1171968
Efficient implementation of DSP applications are critical for many embedded systems. Optimising compilers for application…
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Review
1992
Review
1992
Relaxation processes of vibrationally excited species in the mesosphere and thermosphere
V. I. Lang
Defense, Security, and Sensing
1992
Corpus ID: 123355574
A critical review of rate constants for collisional relaxation processes and spontaneous emission processes in the non-LTE…
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