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Speedup
Known as:
Ideal speedup
, Cache effect
, Linear speedup
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In computer architecture, speedup is a process for increasing the performance between two systems processing the same problem. More technically, it…
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Related topics
Related topics
30 relations
Amdahl's law
Automatic parallelization tool
BLAST
Backtracking
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Broader (1)
Analysis of parallel algorithms
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2012
Highly Cited
2012
Content adaptive prediction unit size decision algorithm for HEVC intra coding
G. Tian
,
S. Goto
Picture Coding Symposium
2012
Corpus ID: 44919310
The quadtree based picture partition scheme in HEVC contributes to significant coding efficiency improvement, especially for high…
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Highly Cited
2011
Highly Cited
2011
Accelerated low-rank visual recovery by random projection
Yadong Mu
,
Jian Dong
,
Xiao-Tong Yuan
,
Shuicheng Yan
Computer Vision and Pattern Recognition
2011
Corpus ID: 17876056
Exact recovery from contaminated visual data plays an important role in various tasks. By assuming the observed data matrix as…
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Highly Cited
2010
Highly Cited
2010
Efficient computer implementation of coupled hydro-thermo-mechanical analysis
J. Kruis
,
T. Koudelka
,
T. Krejčí
Mathematics and Computers in Simulation
2010
Corpus ID: 5311765
Highly Cited
2010
Highly Cited
2010
Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms
Jigang Wu
,
T. Srikanthan
,
Guang Chen
IEEE transactions on computers
2010
Corpus ID: 1256657
Hardware/software (HW/SW) partitioning is one of the key challenges in HW/SW codesign. This paper presents efficient algorithms…
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Highly Cited
2008
Highly Cited
2008
Sliding-Windows for Rapid Object Class Localization: A Parallel Technique
C. Wojek
,
Gyuri Dorkó
,
A. Schulz
,
B. Schiele
DAGM-Symposium
2008
Corpus ID: 37286148
This paper presents a fast object class localization framework implemented on a data parallel architecture currently available in…
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Highly Cited
2007
Highly Cited
2007
Gate Sizing for Cell-Library-Based Designs
Shiyan Hu
,
M. Ketkar
,
Jiang Hu
IEEE Transactions on Computer-Aided Design of…
2007
Corpus ID: 86426
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with…
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Review
2007
Review
2007
Decimal floating-point in z9: An implementation and testing perspective
A. Y. Duale
,
M. H. Decker
,
Hans-Georg Zipperer
,
M. Aharoni
,
Theodore J. Bohizic
IBM Journal of Research and Development
2007
Corpus ID: 17432130
Although decimal arithmetic is widely used in commercial and financial applications, the related computations are handled in…
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Highly Cited
2000
Highly Cited
2000
Point-centered domain decomposition for parallel molecular dynamics simulation
R. Koradia
,
M. Billeterb
,
P. Güntertc
2000
Corpus ID: 14841540
A new algorithm for molecular dynamics simulations of biological macromolecules on parallel computers, point-centered domain…
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Highly Cited
1998
Highly Cited
1998
Parallel 3-D pseudospectral simulation of seismic wave propagation
T. Furumura
,
B. Kennett
,
H. Takenaka
1998
Corpus ID: 31452555
Three-dimensional pseudospectral modeling for a realistic scale problem is still computationally very intensive, even when using…
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Highly Cited
1992
Highly Cited
1992
Presto(protein Engineering Simulator): A Vectorized Molecular Mechanics Program for Biopolymers
K. Morikami
,
T. Nakai
,
A. Kidera
,
M. Saito
,
Haruki Nakamura
Computers and Chemistry
1992
Corpus ID: 40353729
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