• Publications
  • Influence
Computer Architecture: A Quantitative Approach
This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most importantExpand
Computer Architecture - A Quantitative Approach, 5th Edition
TLDR
A quantitative approach to computer architecture a quantitative approach 5th edition computer architecture quantitative approach solution manual computer Architecture quantitative approach solutions manual computer architecture an quantitative approach 3rd editionComputer architecture, fifth edition. Expand
Computer Architecture, Fifth Edition: A Quantitative Approach
TLDR
The Fifth Edition of Computer Architecture focuses on this dramatic shift in the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Expand
Memory consistency and event ordering in scalable shared-memory multiprocessors
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced. A framework for classifying shared accessesExpand
The Stanford Dash multiprocessor
TLDR
The overall goals and major features of the directory architecture for shared memory (Dash), a distributed directory-based protocol that provides cache coherence without compromising scalability, are presented. Expand
SUIF: an infrastructure for research on parallelizing and optimizing compilers
TLDR
The SUIF compiler is built into a powerful, flexible system that may be useful for many other researchers and the authors invite you to use and welcome your contributions to this infrastructure. Expand
Memory consistency and event ordering in scalable shared-memory multiprocessors
TLDR
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced and is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. Expand
The directory-based cache coherence protocol for the DASH multiprocessor
TLDR
The design of the DASH coherence protocol is presented and how it addresses the issues of correctness, performance and protocol complexity are discussed and compared to the IEEE Scalable Coherent Interface protocol. Expand
The Stanford FLASH multiprocessor
The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASHExpand
...
1
2
3
4
5
...