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Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support… Expand In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as… Expand Until recently, a steadily rising clock rate and other uniprocessor micro architectural improvements could be relied upon to… Expand The basic idea behind software pipelining was first developed by Patel and Davidson for scheduling hardware pipe-lines. As… Expand This paper is a scientific comparison of two code generation techniques with identical goals --- generation of the best possible… Expand Utilizing parallelism at the instruction level is an important way to improve performance. Because the time spent in loop… Expand Modulo scheduling is a framework within which a wide variety of algorithms and heuristics may be defined for software pipelining… Expand Although software pipelining has been proposed as one of the most important loop scheduling methods, simultaneous scheduling and… Expand Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops… Expand This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software… Expand